Commit 21642da2 authored by Mark Brown's avatar Mark Brown Committed by Will Deacon
Browse files

arm64/cpufeature: Consistently use symbolic constants for min_field_value 



A number of the cpufeatures use raw numbers for the minimum field values
specified rather than symbolic constants. In preparation for the use of
helper macros replace all these with the appropriate constants.

No change in the generated binary.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230303-arm64-cpufeature-helpers-v2-2-4c8f28a6f203@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 876e3c8e

arch/arm64/kernel/cpufeature.c

+17 −17
Original line number Diff line number Diff line
@@ -2217,7 +2217,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.field_pos = ID_AA64PFR0_EL1_GIC_SHIFT,

		.field_width = 4,

		.sign = FTR_UNSIGNED,

		.min_field_value = 1,

		.min_field_value = ID_AA64PFR0_EL1_GIC_IMP,

	},

	{

		.desc = "Enhanced Counter Virtualization",
@@ -2228,7 +2228,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.field_pos = ID_AA64MMFR0_EL1_ECV_SHIFT,

		.field_width = 4,

		.sign = FTR_UNSIGNED,

		.min_field_value = 1,

		.min_field_value = ID_AA64MMFR0_EL1_ECV_IMP,

	},

#ifdef CONFIG_ARM64_PAN

	{
@@ -2240,7 +2240,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,

		.field_width = 4,

		.sign = FTR_UNSIGNED,

		.min_field_value = 1,

		.min_field_value = ID_AA64MMFR1_EL1_PAN_IMP,

		.cpu_enable = cpu_enable_pan,

	},

#endif /* CONFIG_ARM64_PAN */
@@ -2254,7 +2254,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,

		.field_width = 4,

		.sign = FTR_UNSIGNED,

		.min_field_value = 3,

		.min_field_value = ID_AA64MMFR1_EL1_PAN_PAN3,

	},

#endif /* CONFIG_ARM64_EPAN */

#ifdef CONFIG_ARM64_LSE_ATOMICS
@@ -2267,7 +2267,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT,

		.field_width = 4,

		.sign = FTR_UNSIGNED,

		.min_field_value = 2,

		.min_field_value = ID_AA64ISAR0_EL1_ATOMIC_IMP,

	},

#endif /* CONFIG_ARM64_LSE_ATOMICS */

	{
@@ -2335,7 +2335,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.sys_reg = SYS_ID_AA64PFR0_EL1,

		.field_pos = ID_AA64PFR0_EL1_CSV3_SHIFT,

		.field_width = 4,

		.min_field_value = 1,

		.min_field_value = ID_AA64PFR0_EL1_CSV3_IMP,

		.matches = unmap_kernel_at_el0,

		.cpu_enable = kpti_install_ng_mappings,

	},
@@ -2355,7 +2355,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.sys_reg = SYS_ID_AA64ISAR1_EL1,

		.field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,

		.field_width = 4,

		.min_field_value = 1,

		.min_field_value = ID_AA64ISAR1_EL1_DPB_IMP,

	},

	{

		.desc = "Data cache clean to Point of Deep Persistence",
@@ -2366,7 +2366,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,

		.field_width = 4,

		.min_field_value = 2,

		.min_field_value = ID_AA64ISAR1_EL1_DPB_DPB2,

	},

#endif

#ifdef CONFIG_ARM64_SVE
@@ -2437,7 +2437,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64MMFR2_EL1_FWB_SHIFT,

		.field_width = 4,

		.min_field_value = 1,

		.min_field_value = ID_AA64MMFR2_EL1_FWB_IMP,

		.matches = has_cpuid_feature,

	},

	{
@@ -2448,7 +2448,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64MMFR2_EL1_TTL_SHIFT,

		.field_width = 4,

		.min_field_value = 1,

		.min_field_value = ID_AA64MMFR2_EL1_TTL_IMP,

		.matches = has_cpuid_feature,

	},

	{
@@ -2478,7 +2478,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64MMFR1_EL1_HAFDBS_SHIFT,

		.field_width = 4,

		.min_field_value = 2,

		.min_field_value = ID_AA64MMFR1_EL1_HAFDBS_DBM,

		.matches = has_hw_dbm,

		.cpu_enable = cpu_enable_hw_dbm,

	},
@@ -2491,7 +2491,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.sys_reg = SYS_ID_AA64ISAR0_EL1,

		.field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT,

		.field_width = 4,

		.min_field_value = 1,

		.min_field_value = ID_AA64ISAR0_EL1_CRC32_IMP,

	},

	{

		.desc = "Speculative Store Bypassing Safe (SSBS)",
@@ -2514,7 +2514,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64MMFR2_EL1_CnP_SHIFT,

		.field_width = 4,

		.min_field_value = 1,

		.min_field_value = ID_AA64MMFR2_EL1_CnP_IMP,

		.cpu_enable = cpu_enable_cnp,

	},

#endif
@@ -2527,7 +2527,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.field_pos = ID_AA64ISAR1_EL1_SB_SHIFT,

		.field_width = 4,

		.sign = FTR_UNSIGNED,

		.min_field_value = 1,

		.min_field_value = ID_AA64ISAR1_EL1_SB_IMP,

	},

#ifdef CONFIG_ARM64_PTR_AUTH

	{
@@ -2636,7 +2636,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.field_width = 4,

		.field_pos = ID_AA64MMFR2_EL1_E0PD_SHIFT,

		.matches = has_cpuid_feature,

		.min_field_value = 1,

		.min_field_value = ID_AA64MMFR2_EL1_E0PD_IMP,

		.cpu_enable = cpu_enable_e0pd,

	},

#endif
@@ -2649,7 +2649,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT,

		.field_width = 4,

		.sign = FTR_UNSIGNED,

		.min_field_value = 1,

		.min_field_value = ID_AA64ISAR0_EL1_RNDR_IMP,

	},

#ifdef CONFIG_ARM64_BTI

	{
@@ -2703,7 +2703,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT,

		.field_width = 4,

		.matches = has_cpuid_feature,

		.min_field_value = 1,

		.min_field_value = ID_AA64ISAR1_EL1_LRCPC_IMP,

	},

#ifdef CONFIG_ARM64_SME

	{