Commit 21539b8f authored by Abhinav Kumar's avatar Abhinav Kumar Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: move _dpu_plane_get_qos_lut to dpu_hw_util file 



_dpu_plane_get_qos_lut() is not specific to just dpu_plane.
It can take any fill level and return the LUT matching it.
This can be used even for other modules like dpu_writeback.

Move _dpu_plane_get_qos_lut() to the common dpu_hw_util file
and rename it to _dpu_hw_get_qos_lut().

Signed-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/483518/
Link: https://lore.kernel.org/r/1650984096-9964-13-git-send-email-quic_abhinavk@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent d4e5f450

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

+25 −0
Original line number Diff line number Diff line
@@ -422,3 +422,28 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, 
	DPU_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]);

	DPU_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]);

}



/**

 * _dpu_hw_get_qos_lut - get LUT mapping based on fill level

 * @tbl:		Pointer to LUT table

 * @total_fl:		fill level

 * Return: LUT setting corresponding to the fill level

 */

u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,

		u32 total_fl)

{

	int i;



	if (!tbl || !tbl->nentry || !tbl->entries)

		return 0;



	for (i = 0; i < tbl->nentry; i++)

		if (total_fl <= tbl->entries[i].fl)

			return tbl->entries[i].lut;



	/* if last fl is zero, use as default */

	if (!tbl->entries[i-1].fl)

		return tbl->entries[i-1].lut;



	return 0;

}

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h

+4 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/io.h>

#include <linux/slab.h>

#include "dpu_hw_mdss.h"

#include "dpu_hw_catalog.h"



#define REG_MASK(n)                     ((BIT(n)) - 1)
@@ -339,4 +340,7 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, 
		u32 csc_reg_off,

		const struct dpu_csc_cfg *data, bool csc10);



u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,

		u32 total_fl);



#endif /* _DPU_HW_UTIL_H */

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

+1 −26
Original line number Diff line number Diff line
@@ -279,31 +279,6 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, 
	return total_fl;

}



/**

 * _dpu_plane_get_qos_lut - get LUT mapping based on fill level

 * @tbl:		Pointer to LUT table

 * @total_fl:		fill level

 * Return: LUT setting corresponding to the fill level

 */

static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,

		u32 total_fl)

{

	int i;



	if (!tbl || !tbl->nentry || !tbl->entries)

		return 0;



	for (i = 0; i < tbl->nentry; i++)

		if (total_fl <= tbl->entries[i].fl)

			return tbl->entries[i].lut;



	/* if last fl is zero, use as default */

	if (!tbl->entries[i-1].fl)

		return tbl->entries[i-1].lut;



	return 0;

}



/**

 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane

 * @plane:		Pointer to drm plane
@@ -333,7 +308,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, 
			lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;

	}



	qos_lut = _dpu_plane_get_qos_lut(

	qos_lut = _dpu_hw_get_qos_lut(

			&pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl);



	trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,