Commit 213e1220 authored by Bharat Kumar Gogada's avatar Bharat Kumar Gogada Committed by Lorenzo Pieralisi
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PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI 

Add support for routing PCIe DMA traffic coherently when
Cache Coherent Interconnect (CCI) is enabled in the system.
The "dma-coherent" property is used to determine if CCI is enabled
or not.
Refer to https://developer.arm.com/documentation/ddi0470/k/preface
for the CCI specification.

Link: https://lore.kernel.org/r/20210222084732.21521-1-bharat.kumar.gogada@xilinx.com


Signed-off-by: default avatarBharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
parent a38fd874

drivers/pci/controller/pcie-xilinx-nwl.c

+7 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 


/* Bridge core config registers */

#define BRCFG_PCIE_RX0			0x00000000

#define BRCFG_PCIE_RX1			0x00000004

#define BRCFG_INTERRUPT			0x00000010

#define BRCFG_PCIE_RX_MSG_FILTER	0x00000020
@@ -128,6 +129,7 @@ 
#define NWL_ECAM_VALUE_DEFAULT		12



#define CFG_DMA_REG_BAR			GENMASK(2, 0)

#define CFG_PCIE_CACHE			GENMASK(7, 0)



#define INT_PCI_MSI_NR			(2 * 32)
@@ -675,6 +677,11 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) 
	nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,

			  BRCFG_PCIE_RX_MSG_FILTER);



	/* This routes the PCIe DMA traffic to go through CCI path */

	if (of_dma_is_coherent(dev->of_node))

		nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |

				  CFG_PCIE_CACHE, BRCFG_PCIE_RX1);



	err = nwl_wait_for_link(pcie);

	if (err)

		return err;