Commit 211ec660 authored by Dave Jiang's avatar Dave Jiang Committed by Zheng Wu
Browse files

ntb: intel: add GNR support for Intel PCIe gen5 NTB 

mainline inclusion
from mainline-v6.0-rc1
commit a914fc52
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8KPHC



-------------------------------------

Intel-SIG: commit a914fc52 ntb: intel: add GNR support for Intel
PCIe gen5 NTB.
Backport Intel NTB GNR support patch.

-------------------------------------

[ Upstream commit a914fc52 ]

Add Intel Granite Rapids NTB PCI device ID and related enabling.
Expectation is same hardware interface as Saphire Rapids Xeon platforms.

Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Acked-by: default avatarAllen Hubbe <allenbh@gmail.com>
Signed-off-by: default avatarJon Mason <jdmason@kudzu.us>
[ Zheng Wu: amend commit log ]
Signed-off-by: default avatarZheng Wu <wu.zheng@intel.com>
parent 122be423

drivers/ntb/hw/intel/ntb_hw_gen1.c

+8 −4
Original line number Diff line number Diff line
@@ -763,7 +763,7 @@ static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf, 
		return ndev_ntb_debugfs_read(filp, ubuf, count, offp);

	else if (pdev_is_gen3(ndev->ntb.pdev))

		return ndev_ntb3_debugfs_read(filp, ubuf, count, offp);

	else if (pdev_is_gen4(ndev->ntb.pdev))

	else if (pdev_is_gen4(ndev->ntb.pdev) || pdev_is_gen5(ndev->ntb.pdev))

		return ndev_ntb4_debugfs_read(filp, ubuf, count, offp);



	return -ENXIO;
@@ -1882,7 +1882,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, 
		rc = gen3_init_dev(ndev);

		if (rc)

			goto err_init_dev;

	} else if (pdev_is_gen4(pdev)) {

	} else if (pdev_is_gen4(pdev) || pdev_is_gen5(pdev)) {

		ndev->ntb.ops = &intel_ntb4_ops;

		rc = intel_ntb_init_pci(ndev, pdev);

		if (rc)
@@ -1912,7 +1912,8 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, 


err_register:

	ndev_deinit_debugfs(ndev);

	if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || pdev_is_gen4(pdev))

	if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) ||

	    pdev_is_gen4(pdev) || pdev_is_gen5(pdev))

		xeon_deinit_dev(ndev);

err_init_dev:

	intel_ntb_deinit_pci(ndev);
@@ -1928,7 +1929,8 @@ static void intel_ntb_pci_remove(struct pci_dev *pdev) 


	ntb_unregister_device(&ndev->ntb);

	ndev_deinit_debugfs(ndev);

	if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || pdev_is_gen4(pdev))

	if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) ||

	    pdev_is_gen4(pdev) || pdev_is_gen5(pdev))

		xeon_deinit_dev(ndev);

	intel_ntb_deinit_pci(ndev);

	kfree(ndev);
@@ -2055,6 +2057,8 @@ static const struct pci_device_id intel_ntb_pci_tbl[] = { 


	/* GEN4 */

	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)},

	/* GEN5 PCIe */

	{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_GNR)},

	{0}

};

MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl);

drivers/ntb/hw/intel/ntb_hw_gen4.c

+1 −1
Original line number Diff line number Diff line
@@ -197,7 +197,7 @@ int gen4_init_dev(struct intel_ntb_dev *ndev) 
	ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET);

	if (pdev_is_ICX(pdev))

		ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1);

	else if (pdev_is_SPR(pdev))

	else if (pdev_is_SPR(pdev) || pdev_is_gen5(pdev))

		ndev->ntb.topo = spr_ppd_topo(ndev, ppd1);

	dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd1,

		ntb_topo_string(ndev->ntb.topo));

drivers/ntb/hw/intel/ntb_hw_intel.h

+7 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ 
#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX	0x6F0F

#define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX	0x201C

#define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX	0x347e

#define PCI_DEVICE_ID_INTEL_NTB_B2B_GNR	0x0db4



/* Ntb control and link status */

#define NTB_CTL_CFG_LOCK		BIT(0)
@@ -231,4 +232,10 @@ static inline int pdev_is_gen4(struct pci_dev *pdev) 


	return 0;

}



static inline int pdev_is_gen5(struct pci_dev *pdev)

{

	return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR;

}



#endif