Commit 2110add8 authored by Xingyu Wu's avatar Xingyu Wu Committed by Conor Dooley
Browse files

dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs 



Add PLL clock inputs from PLL clock generator.

Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarXingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent c81f7845

Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml

+16 −2
Original line number Diff line number Diff line
@@ -27,6 +27,9 @@ properties: 
          - description: External I2S RX left/right channel clock

          - description: External TDM clock

          - description: External audio master clock

          - description: PLL0

          - description: PLL1

          - description: PLL2



      - items:

          - description: Main Oscillator (24 MHz)
@@ -38,6 +41,9 @@ properties: 
          - description: External I2S RX left/right channel clock

          - description: External TDM clock

          - description: External audio master clock

          - description: PLL0

          - description: PLL1

          - description: PLL2



  clock-names:

    oneOf:
@@ -52,6 +58,9 @@ properties: 
          - const: i2srx_lrck_ext

          - const: tdm_ext

          - const: mclk_ext

          - const: pll0_out

          - const: pll1_out

          - const: pll2_out



      - items:

          - const: osc
@@ -63,6 +72,9 @@ properties: 
          - const: i2srx_lrck_ext

          - const: tdm_ext

          - const: mclk_ext

          - const: pll0_out

          - const: pll1_out

          - const: pll2_out



  '#clock-cells':

    const: 1
@@ -93,12 +105,14 @@ examples: 
                 <&gmac1_rgmii_rxin>,

                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,

                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,

                 <&tdm_ext>, <&mclk_ext>;

                 <&tdm_ext>, <&mclk_ext>,

                 <&pllclk 0>, <&pllclk 1>, <&pllclk 2>;

        clock-names = "osc", "gmac1_rmii_refin",

                      "gmac1_rgmii_rxin",

                      "i2stx_bclk_ext", "i2stx_lrck_ext",

                      "i2srx_bclk_ext", "i2srx_lrck_ext",

                      "tdm_ext", "mclk_ext";

                      "tdm_ext", "mclk_ext",

                      "pll0_out", "pll1_out", "pll2_out";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };