Commit 20cddfcc authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by Rodrigo Vivi
Browse files

drm/i915/gt: Use hw_engine_masks as reset_domains 



We need a way to reset engines by their reset domains.
This change sets up way to fetch reset domains of each
engine globally.

Changes since V1:
	- Use static reset domain array - Ville and Tvrtko
	- Use BUG_ON at appropriate place - Tvrtko

Signed-off-by: default avatarTejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211206081026.4024401-1-tejaskumarx.surendrakumar.upadhyay@intel.com
parent 97c8ef44

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+32 −0
Original line number Diff line number Diff line
@@ -325,6 +325,38 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, 
	engine->id = id;

	engine->legacy_idx = INVALID_ENGINE;

	engine->mask = BIT(id);

	if (GRAPHICS_VER(gt->i915) >= 11) {

		static const u32 engine_reset_domains[] = {

			[RCS0]  = GEN11_GRDOM_RENDER,

			[BCS0]  = GEN11_GRDOM_BLT,

			[VCS0]  = GEN11_GRDOM_MEDIA,

			[VCS1]  = GEN11_GRDOM_MEDIA2,

			[VCS2]  = GEN11_GRDOM_MEDIA3,

			[VCS3]  = GEN11_GRDOM_MEDIA4,

			[VCS4]  = GEN11_GRDOM_MEDIA5,

			[VCS5]  = GEN11_GRDOM_MEDIA6,

			[VCS6]  = GEN11_GRDOM_MEDIA7,

			[VCS7]  = GEN11_GRDOM_MEDIA8,

			[VECS0] = GEN11_GRDOM_VECS,

			[VECS1] = GEN11_GRDOM_VECS2,

			[VECS2] = GEN11_GRDOM_VECS3,

			[VECS3] = GEN11_GRDOM_VECS4,

		};

		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||

			   !engine_reset_domains[id]);

		engine->reset_domain = engine_reset_domains[id];

	} else {

		static const u32 engine_reset_domains[] = {

			[RCS0]  = GEN6_GRDOM_RENDER,

			[BCS0]  = GEN6_GRDOM_BLT,

			[VCS0]  = GEN6_GRDOM_MEDIA,

			[VCS1]  = GEN8_GRDOM_MEDIA2,

			[VECS0] = GEN6_GRDOM_VECS,

		};

		GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||

			   !engine_reset_domains[id]);

		engine->reset_domain = engine_reset_domains[id];

	}

	engine->i915 = i915;

	engine->gt = gt;

	engine->uncore = gt->uncore;

drivers/gpu/drm/i915/gt/intel_engine_types.h

+1 −0
Original line number Diff line number Diff line
@@ -318,6 +318,7 @@ struct intel_engine_cs { 
	unsigned int guc_id;



	intel_engine_mask_t mask;

	u32 reset_domain;

	/**

	 * @logical_mask: logical mask of engine, reported to user space via

	 * query IOCTL and used to communicate with the GuC in logical space.

drivers/gpu/drm/i915/gt/intel_reset.c

+2 −27
Original line number Diff line number Diff line
@@ -297,13 +297,6 @@ static int gen6_reset_engines(struct intel_gt *gt, 
			      intel_engine_mask_t engine_mask,

			      unsigned int retry)

{

	static const u32 hw_engine_mask[] = {

		[RCS0]  = GEN6_GRDOM_RENDER,

		[BCS0]  = GEN6_GRDOM_BLT,

		[VCS0]  = GEN6_GRDOM_MEDIA,

		[VCS1]  = GEN8_GRDOM_MEDIA2,

		[VECS0] = GEN6_GRDOM_VECS,

	};

	struct intel_engine_cs *engine;

	u32 hw_mask;
@@ -314,8 +307,7 @@ static int gen6_reset_engines(struct intel_gt *gt, 


		hw_mask = 0;

		for_each_engine_masked(engine, gt, engine_mask, tmp) {

			GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));

			hw_mask |= hw_engine_mask[engine->id];

			hw_mask |= engine->reset_domain;

		}

	}
@@ -492,22 +484,6 @@ static int gen11_reset_engines(struct intel_gt *gt, 
			       intel_engine_mask_t engine_mask,

			       unsigned int retry)

{

	static const u32 hw_engine_mask[] = {

		[RCS0]  = GEN11_GRDOM_RENDER,

		[BCS0]  = GEN11_GRDOM_BLT,

		[VCS0]  = GEN11_GRDOM_MEDIA,

		[VCS1]  = GEN11_GRDOM_MEDIA2,

		[VCS2]  = GEN11_GRDOM_MEDIA3,

		[VCS3]  = GEN11_GRDOM_MEDIA4,

		[VCS4]  = GEN11_GRDOM_MEDIA5,

		[VCS5]  = GEN11_GRDOM_MEDIA6,

		[VCS6]  = GEN11_GRDOM_MEDIA7,

		[VCS7]  = GEN11_GRDOM_MEDIA8,

		[VECS0] = GEN11_GRDOM_VECS,

		[VECS1] = GEN11_GRDOM_VECS2,

		[VECS2] = GEN11_GRDOM_VECS3,

		[VECS3] = GEN11_GRDOM_VECS4,

	};

	struct intel_engine_cs *engine;

	intel_engine_mask_t tmp;

	u32 reset_mask, unlock_mask = 0;
@@ -518,8 +494,7 @@ static int gen11_reset_engines(struct intel_gt *gt, 
	} else {

		reset_mask = 0;

		for_each_engine_masked(engine, gt, engine_mask, tmp) {

			GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));

			reset_mask |= hw_engine_mask[engine->id];

			reset_mask |= engine->reset_domain;

			ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask);

			if (ret)

				goto sfc_unlock;