Commit 20cc05ba authored by Takeshi Kihara's avatar Takeshi Kihara Committed by Geert Uytterhoeven
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clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor 



Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed
divisor other than 2, the value used by all such clocks supported to date.

This is in preparation for supporting the Z2 clock on the R-Car E3
(r8a77990) SoC which has a fixed divisor of 4.

Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: squashed several patches; rewrote changelog; added r8a774a1 change]
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 1addd6d5

drivers/clk/renesas/r8a774a1-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { 
	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),



	/* Core Clock Outputs */

	DEF_BASE("z",           R8A774A1_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),

	DEF_BASE("z2",          R8A774A1_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),

	DEF_GEN3_Z("z",		R8A774A1_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0, 2),

	DEF_GEN3_Z("z2",	R8A774A1_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2),

	DEF_FIXED("ztr",        R8A774A1_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A774A1_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),

drivers/clk/renesas/r8a7795-cpg-mssr.c

+3 −2
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset

 *

 * Copyright (C) 2015 Glider bvba

 * Copyright (C) 2018 Renesas Electronics Corp.

 *

 * Based on clk-rcar-gen3.c

 *
@@ -73,8 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { 
	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),



	/* Core Clock Outputs */

	DEF_BASE("z",           R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),

	DEF_BASE("z2",          R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),

	DEF_GEN3_Z("z",         R8A7795_CLK_Z,	   CLK_TYPE_GEN3_Z,  CLK_PLL0, 2),

	DEF_GEN3_Z("z2",        R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2),

	DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),

drivers/clk/renesas/r8a7796-cpg-mssr.c

+3 −2
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset

 *

 * Copyright (C) 2016 Glider bvba

 * Copyright (C) 2018 Renesas Electronics Corp.

 *

 * Based on r8a7795-cpg-mssr.c

 *
@@ -73,8 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 
	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),



	/* Core Clock Outputs */

	DEF_BASE("z",           R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),

	DEF_BASE("z2",          R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),

	DEF_GEN3_Z("z",         R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2),

	DEF_GEN3_Z("z2",        R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2),

	DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),

drivers/clk/renesas/r8a77965-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { 
	DEF_GEN3_OSC(".r",	CLK_RINT,		CLK_EXTAL,	32),



	/* Core Clock Outputs */

	DEF_BASE("z",		R8A77965_CLK_Z,		CLK_TYPE_GEN3_Z, CLK_PLL0),

	DEF_GEN3_Z("z",		R8A77965_CLK_Z,		CLK_TYPE_GEN3_Z,  CLK_PLL0, 2),

	DEF_FIXED("ztr",	R8A77965_CLK_ZTR,	CLK_PLL1_DIV2,	6, 1),

	DEF_FIXED("ztrd2",	R8A77965_CLK_ZTRD2,	CLK_PLL1_DIV2,	12, 1),

	DEF_FIXED("zt",		R8A77965_CLK_ZT,	CLK_PLL1_DIV2,	4, 1),

drivers/clk/renesas/rcar-gen3-cpg.c

+15 −9
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ struct cpg_z_clk { 
	void __iomem *reg;

	void __iomem *kick_reg;

	unsigned long mask;

	unsigned int fixed_div;

};



#define to_z_clk(_hw)	container_of(_hw, struct cpg_z_clk, hw)
@@ -110,17 +111,18 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, 
	val = readl(zclk->reg) & zclk->mask;

	mult = 32 - (val >> __ffs(zclk->mask));



	/* Factor of 2 is for fixed divider */

	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2);

	return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,

				     32 * zclk->fixed_div);

}



static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,

				 unsigned long *parent_rate)

{

	/* Factor of 2 is for fixed divider */

	unsigned long prate = *parent_rate / 2;

	struct cpg_z_clk *zclk = to_z_clk(hw);

	unsigned long prate;

	unsigned int mult;



	prate = *parent_rate / zclk->fixed_div;

	mult = div_u64(rate * 32ULL, prate);

	mult = clamp(mult, 1U, 32U);
@@ -134,8 +136,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, 
	unsigned int mult;

	unsigned int i;



	/* Factor of 2 is for fixed divider */

	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);

	mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * zclk->fixed_div,

				     parent_rate);

	mult = clamp(mult, 1U, 32U);



	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
@@ -178,7 +180,8 @@ static const struct clk_ops cpg_z_clk_ops = { 
static struct clk * __init cpg_z_clk_register(const char *name,

					      const char *parent_name,

					      void __iomem *reg,

					      unsigned long mask)

					      unsigned long mask,

					      unsigned int div)

{

	struct clk_init_data init;

	struct cpg_z_clk *zclk;
@@ -198,6 +201,7 @@ static struct clk * __init cpg_z_clk_register(const char *name, 
	zclk->kick_reg = reg + CPG_FRQCRB;

	zclk->hw.init = &init;

	zclk->mask = mask;

	zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */



	clk = clk_register(NULL, &zclk->hw);

	if (IS_ERR(clk))
@@ -658,11 +662,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 


	case CLK_TYPE_GEN3_Z:

		return cpg_z_clk_register(core->name, __clk_get_name(parent),

					  base, CPG_FRQCRC_ZFC_MASK);

					  base, CPG_FRQCRC_ZFC_MASK,

					  core->div);



	case CLK_TYPE_GEN3_Z2:

		return cpg_z_clk_register(core->name, __clk_get_name(parent),

					  base, CPG_FRQCRC_Z2FC_MASK);

					  base, CPG_FRQCRC_Z2FC_MASK,

					  core->div);



	case CLK_TYPE_GEN3_OSC:

		/*