Unverified Commit 20c05a05 authored by Vladimir Oltean's avatar Vladimir Oltean Committed by Mark Brown
Browse files

spi: spi-fsl-dspi: delete EOQ transfer mode 



After the only user of the limited EOQ mode has now been converted to
DMA as of commit b09058bb ("spi: spi-fsl-dspi: set ColdFire to DMA
mode"), we can finally delete this code.

Signed-off-by: default avatarVladimir Oltean <olteanv@gmail.com>
Link: https://lore.kernel.org/r/20200823212657.2400075-1-olteanv@gmail.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 6a23e577

drivers/spi/spi-fsl-dspi.c

+5 −51
Original line number Diff line number Diff line
@@ -53,7 +53,6 @@ 


#define SPI_SR				0x2c

#define SPI_SR_TCFQF			BIT(31)

#define SPI_SR_EOQF			BIT(28)

#define SPI_SR_TFUF			BIT(27)

#define SPI_SR_TFFF			BIT(25)

#define SPI_SR_CMDTCF			BIT(23)
@@ -62,7 +61,7 @@ 
#define SPI_SR_TFIWF			BIT(18)

#define SPI_SR_RFDF			BIT(17)

#define SPI_SR_CMDFFF			BIT(16)

#define SPI_SR_CLEAR			(SPI_SR_TCFQF | SPI_SR_EOQF | \

#define SPI_SR_CLEAR			(SPI_SR_TCFQF | \

					SPI_SR_TFUF | SPI_SR_TFFF | \

					SPI_SR_CMDTCF | SPI_SR_SPEF | \

					SPI_SR_RFOF | SPI_SR_TFIWF | \
@@ -75,7 +74,6 @@ 


#define SPI_RSER			0x30

#define SPI_RSER_TCFQE			BIT(31)

#define SPI_RSER_EOQFE			BIT(28)

#define SPI_RSER_CMDTCFE		BIT(23)



#define SPI_PUSHR			0x34
@@ -114,7 +112,6 @@ struct chip_data { 
};



enum dspi_trans_mode {

	DSPI_EOQ_MODE = 0,

	DSPI_XSPI_MODE,

	DSPI_DMA_MODE,

};
@@ -671,11 +668,6 @@ static void ns_delay_scale(char *psc, char *sc, int delay_ns, 
	}

}



static void dspi_pushr_write(struct fsl_dspi *dspi)

{

	regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi));

}



static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd)

{

	/*
@@ -735,21 +727,6 @@ static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words) 
	}

}



static void dspi_eoq_fifo_write(struct fsl_dspi *dspi, int num_words)

{

	u16 xfer_cmd = dspi->tx_cmd;



	/* Fill TX FIFO with as many transfers as possible */

	while (num_words--) {

		dspi->tx_cmd = xfer_cmd;

		/* Request EOQF for last transfer in FIFO */

		if (num_words == 0)

			dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ;

		/* Write combined TX FIFO and CMD FIFO entry */

		dspi_pushr_write(dspi);

	}

}



static u32 dspi_popr_read(struct fsl_dspi *dspi)

{

	u32 rxdata = 0;
@@ -818,7 +795,7 @@ static void dspi_setup_accel(struct fsl_dspi *dspi) 
	dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8);



	/*

	 * Update CTAR here (code is common for EOQ, XSPI and DMA modes).

	 * Update CTAR here (code is common for XSPI and DMA modes).

	 * We will update CTARE in the portion specific to XSPI, when we

	 * also know the preload value (DTCP).

	 */
@@ -862,9 +839,6 @@ static void dspi_fifo_write(struct fsl_dspi *dspi) 


	spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq);



	if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE)

		dspi_eoq_fifo_write(dspi, num_words);

	else

	dspi_xspi_fifo_write(dspi, num_words);

	/*

	 * Everything after this point is in a potential race with the next
@@ -898,7 +872,7 @@ static int dspi_poll(struct fsl_dspi *dspi) 
		regmap_read(dspi->regmap, SPI_SR, &spi_sr);

		regmap_write(dspi->regmap, SPI_SR, spi_sr);



		if (spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF))

		if (spi_sr & SPI_SR_CMDTCF)

			break;

	} while (--tries);
@@ -916,7 +890,7 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id) 
	regmap_read(dspi->regmap, SPI_SR, &spi_sr);

	regmap_write(dspi->regmap, SPI_SR, spi_sr);



	if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF)))

	if (!(spi_sr & SPI_SR_CMDTCF))

		return IRQ_NONE;



	if (dspi_rxtx(dspi) == 0)
@@ -1204,9 +1178,6 @@ static int dspi_init(struct fsl_dspi *dspi) 
	regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);



	switch (dspi->devtype_data->trans_mode) {

	case DSPI_EOQ_MODE:

		regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);

		break;

	case DSPI_XSPI_MODE:

		regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE);

		break;
@@ -1245,22 +1216,6 @@ static int dspi_slave_abort(struct spi_master *master) 
	return 0;

}



/*

 * EOQ mode will inevitably deassert its PCS signal on last word in a queue

 * (hardware limitation), so we need to inform the spi_device that larger

 * buffers than the FIFO size are going to have the chip select randomly

 * toggling, so it has a chance to adapt its message sizes.

 */

static size_t dspi_max_message_size(struct spi_device *spi)

{

	struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);



	if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE)

		return dspi->devtype_data->fifo_size;



	return SIZE_MAX;

}



static int dspi_probe(struct platform_device *pdev)

{

	struct device_node *np = pdev->dev.of_node;
@@ -1283,7 +1238,6 @@ static int dspi_probe(struct platform_device *pdev) 


	ctlr->setup = dspi_setup;

	ctlr->transfer_one_message = dspi_transfer_one_message;

	ctlr->max_message_size = dspi_max_message_size;

	ctlr->dev.of_node = pdev->dev.of_node;



	ctlr->cleanup = dspi_cleanup;