Commit 2081076a authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'sti-soc-for-v4.21-round1' of... 

Merge tag 'sti-soc-for-v4.21-round1' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/late

Highlights:
-----------
- Following pen_release and boot_lock cleanup initiated by
  Russell King, .smp_prepare_cpus and .smp_boot_secondary STi callbacks
  must be reworked to keep secondary CPU's bringup.

* tag 'sti-soc-for-v4.21-round1' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti

:
  ARM: sti: remove pen_release and boot_lock

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 8a66c20e 704cfd7f

arch/arm/mach-sti/Makefile

+1 −1
Original line number Diff line number Diff line 
obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o

obj-$(CONFIG_SMP)		+= platsmp.o

obj-$(CONFIG_ARCH_STI) 		+= board-dt.o

arch/arm/mach-sti/headsmp.S

deleted100644 → 0
+0 −43
Original line number Diff line number Diff line 
/*

 *  arch/arm/mach-sti/headsmp.S

 *

 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.

 *		http://www.st.com

 *

 * Cloned from linux/arch/arm/mach-vexpress/headsmp.S

 *

 *  Copyright (c) 2003 ARM Limited

 *  All Rights Reserved

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

#include <linux/linkage.h>

#include <linux/init.h>



/*

 * ST specific entry point for secondary CPUs.  This provides

 * a "holding pen" into which all secondary cores are held until we're

 * ready for them to initialise.

 */

ENTRY(sti_secondary_startup)

	mrc	p15, 0, r0, c0, c0, 5

	and	r0, r0, #15

	adr	r4, 1f

	ldmia	r4, {r5, r6}

	sub	r4, r4, r5

	add	r6, r6, r4

pen:	ldr	r7, [r6]

	cmp	r7, r0

	bne	pen



	/*

	 * we've been released from the holding pen: secondary_stack

	 * should now contain the SVC stack for this core

	 */

	b	secondary_startup

ENDPROC(sti_secondary_startup)



1:	.long	.

	.long	pen_release

arch/arm/mach-sti/platsmp.c

+14 −74
Original line number Diff line number Diff line
@@ -28,82 +28,33 @@ 


#include "smp.h"



static void write_pen_release(int val)

{

	pen_release = val;

	smp_wmb();

	sync_cache_w(&pen_release);

}



static DEFINE_SPINLOCK(boot_lock);



static void sti_secondary_init(unsigned int cpu)

{

	/*

	 * let the primary processor know we're out of the

	 * pen, then head off into the C entry point

	 */

	write_pen_release(-1);



	/*

	 * Synchronise with the boot thread.

	 */

	spin_lock(&boot_lock);

	spin_unlock(&boot_lock);

}

static u32 __iomem *cpu_strt_ptr;



static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)

{

	unsigned long timeout;

	unsigned long entry_pa = __pa_symbol(secondary_startup);



	/*

	 * set synchronisation state between this boot processor

	 * and the secondary one

	 * Secondary CPU is initialised and started by a U-BOOTROM firmware.

	 * Secondary CPU is spinning and waiting for a write at cpu_strt_ptr.

	 * Writing secondary_startup address at cpu_strt_ptr makes it to

	 * jump directly to secondary_startup().

	 */

	spin_lock(&boot_lock);



	/*

	 * The secondary processor is waiting to be released from

	 * the holding pen - release it, then wait for it to flag

	 * that it has been released by resetting pen_release.

	 *

	 * Note that "pen_release" is the hardware CPU ID, whereas

	 * "cpu" is Linux's internal ID.

	 */

	write_pen_release(cpu_logical_map(cpu));



	/*

	 * Send the secondary CPU a soft interrupt, thereby causing

	 * it to jump to the secondary entrypoint.

	 */

	arch_send_wakeup_ipi_mask(cpumask_of(cpu));



	timeout = jiffies + (1 * HZ);

	while (time_before(jiffies, timeout)) {

		smp_rmb();

		if (pen_release == -1)

			break;



		udelay(10);

	}

	__raw_writel(entry_pa, cpu_strt_ptr);



	/*

	 * now the secondary core is starting up let it run its

	 * calibrations, then wait for it to finish

	 */

	spin_unlock(&boot_lock);

	/* wmb so that data is actually written before cache flush is done */

	smp_wmb();

	sync_cache_w(cpu_strt_ptr);



	return pen_release != -1 ? -ENOSYS : 0;

	return 0;

}



static void __init sti_smp_prepare_cpus(unsigned int max_cpus)

{

	struct device_node *np;

	void __iomem *scu_base;

	u32 __iomem *cpu_strt_ptr;

	u32 release_phys;

	int cpu;

	unsigned long entry_pa = __pa_symbol(sti_secondary_startup);



	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
@@ -131,8 +82,8 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus) 
		}



		/*

		 * holding pen is usually configured in SBC DMEM but can also be

		 * in RAM.

		 * cpu-release-addr is usually configured in SBC DMEM but can

		 * also be in RAM.

		 */



		if (!memblock_is_memory(release_phys))
@@ -142,22 +93,11 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus) 
			cpu_strt_ptr =

				(u32 __iomem *)phys_to_virt(release_phys);



		__raw_writel(entry_pa, cpu_strt_ptr);



		/*

		 * wmb so that data is actually written

		 * before cache flush is done

		 */

		smp_wmb();

		sync_cache_w(cpu_strt_ptr);



		if (!memblock_is_memory(release_phys))

			iounmap(cpu_strt_ptr);

		set_cpu_possible(cpu, true);

	}

}



const struct smp_operations sti_smp_ops __initconst = {

	.smp_prepare_cpus	= sti_smp_prepare_cpus,

	.smp_secondary_init	= sti_secondary_init,

	.smp_boot_secondary	= sti_boot_secondary,

};