Commit 2057b8b7 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'axienet-napi-gro-support'



Robert Hancock says:

====================
NAPI/GRO support for axienet driver

Add support for NAPI and GRO receive in the Xilinx AXI Ethernet driver,
and some other related cleanups.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents c409f9b9 0b79b8dc
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+14 −4
Original line number Diff line number Diff line
@@ -119,11 +119,11 @@
#define XAXIDMA_IRQ_ERROR_MASK		0x00004000 /* Error interrupt */
#define XAXIDMA_IRQ_ALL_MASK		0x00007000 /* All interrupts */

/* Default TX/RX Threshold and waitbound values for SGDMA mode */
/* Default TX/RX Threshold and delay timer values for SGDMA mode */
#define XAXIDMA_DFT_TX_THRESHOLD	24
#define XAXIDMA_DFT_TX_WAITBOUND	254
#define XAXIDMA_DFT_RX_THRESHOLD	24
#define XAXIDMA_DFT_RX_WAITBOUND	254
#define XAXIDMA_DFT_TX_USEC		50
#define XAXIDMA_DFT_RX_THRESHOLD	1
#define XAXIDMA_DFT_RX_USEC		50

#define XAXIDMA_BD_CTRL_TXSOF_MASK	0x08000000 /* First tx packet */
#define XAXIDMA_BD_CTRL_TXEOF_MASK	0x04000000 /* Last tx packet */
@@ -385,6 +385,7 @@ struct axidma_bd {
 * @phy_node:	Pointer to device node structure
 * @phylink:	Pointer to phylink instance
 * @phylink_config: phylink configuration settings
 * @napi:	NAPI control structure
 * @pcs_phy:	Reference to PCS/PMA PHY if used
 * @pcs:	phylink pcs structure for PCS PHY
 * @switch_x_sgmii: Whether switchable 1000BaseX/SGMII mode is enabled in the core
@@ -395,6 +396,7 @@ struct axidma_bd {
 * @regs_start: Resource start for axienet device addresses
 * @regs:	Base address for the axienet_local device address space
 * @dma_regs:	Base address for the axidma device address space
 * @rx_dma_cr:  Nominal content of RX DMA control register
 * @dma_err_task: Work structure to process Axi DMA errors
 * @tx_irq:	Axidma TX IRQ number
 * @rx_irq:	Axidma RX IRQ number
@@ -423,7 +425,9 @@ struct axidma_bd {
 * @csum_offload_on_tx_path:	Stores the checksum selection on TX side.
 * @csum_offload_on_rx_path:	Stores the checksum selection on RX side.
 * @coalesce_count_rx:	Store the irq coalesce on RX side.
 * @coalesce_usec_rx:	IRQ coalesce delay for RX
 * @coalesce_count_tx:	Store the irq coalesce on TX side.
 * @coalesce_usec_tx:	IRQ coalesce delay for TX
 */
struct axienet_local {
	struct net_device *ndev;
@@ -434,6 +438,8 @@ struct axienet_local {
	struct phylink *phylink;
	struct phylink_config phylink_config;

	struct napi_struct napi;

	struct mdio_device *pcs_phy;
	struct phylink_pcs pcs;

@@ -449,6 +455,8 @@ struct axienet_local {
	void __iomem *regs;
	void __iomem *dma_regs;

	u32 rx_dma_cr;

	struct work_struct dma_err_task;

	int tx_irq;
@@ -476,7 +484,9 @@ struct axienet_local {
	int csum_offload_on_rx_path;

	u32 coalesce_count_rx;
	u32 coalesce_usec_rx;
	u32 coalesce_count_tx;
	u32 coalesce_usec_tx;
};

/**
+252 −246

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