Commit 205737fe authored by Jonathan Marek's avatar Jonathan Marek Committed by Bjorn Andersson
Browse files

clk: qcom: add support for SM8350 DISPCC 



Add support to the SM8350 display clock controller by extending the SM8250
display clock controller, which is almost identical but has some minor
differences.

Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Signed-off-by: default avatarRobert Foss <robert.foss@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706154337.2026269-5-robert.foss@linaro.org
parent 160758b0

drivers/clk/qcom/Kconfig

+3 −3
Original line number Diff line number Diff line
@@ -626,11 +626,11 @@ config SM_DISPCC_6125 
	  splash screen



config SM_DISPCC_8250

	tristate "SM8150 and SM8250 Display Clock Controller"

	depends on SM_GCC_8150 || SM_GCC_8250

	tristate "SM8150/SM8250/SM8350 Display Clock Controller"

	depends on SM_GCC_8150 || SM_GCC_8250 || SM_GCC_8350

	help

	  Support for the display clock controller on Qualcomm Technologies, Inc

	  SM8150 and SM8250 devices.

	  SM8150/SM8250/SM8350 devices.

	  Say Y if you want to support display devices and functionality such as

	  splash screen.

drivers/clk/qcom/dispcc-sm8250.c

+62 −1
Original line number Diff line number Diff line
@@ -43,6 +43,10 @@ static struct pll_vco vco_table[] = { 
	{ 249600000, 2000000000, 0 },

};



static struct pll_vco lucid_5lpe_vco[] = {

	{ 249600000, 1750000000, 0 },

};



static struct alpha_pll_config disp_cc_pll0_config = {

	.l = 0x47,

	.alpha = 0xE000,
@@ -1228,6 +1232,7 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = { 
	{ .compatible = "qcom,sc8180x-dispcc" },

	{ .compatible = "qcom,sm8150-dispcc" },

	{ .compatible = "qcom,sm8250-dispcc" },

	{ .compatible = "qcom,sm8350-dispcc" },

	{ }

};

MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
@@ -1258,7 +1263,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) 
		return PTR_ERR(regmap);

	}



	/* note: trion == lucid, except for the prepare() op */

	/* Apply differences for SM8150 and SM8350 */

	BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);

	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||

	    of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
@@ -1270,6 +1275,62 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) 
		disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;

		disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;

		disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;

	} else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {

		static struct clk_rcg2 * const rcgs[] = {

			&disp_cc_mdss_byte0_clk_src,

			&disp_cc_mdss_byte1_clk_src,

			&disp_cc_mdss_dp_aux1_clk_src,

			&disp_cc_mdss_dp_aux_clk_src,

			&disp_cc_mdss_dp_link1_clk_src,

			&disp_cc_mdss_dp_link_clk_src,

			&disp_cc_mdss_dp_pixel1_clk_src,

			&disp_cc_mdss_dp_pixel2_clk_src,

			&disp_cc_mdss_dp_pixel_clk_src,

			&disp_cc_mdss_esc0_clk_src,

			&disp_cc_mdss_mdp_clk_src,

			&disp_cc_mdss_pclk0_clk_src,

			&disp_cc_mdss_pclk1_clk_src,

			&disp_cc_mdss_rot_clk_src,

			&disp_cc_mdss_vsync_clk_src,

		};

		static struct clk_regmap_div * const divs[] = {

			&disp_cc_mdss_byte0_div_clk_src,

			&disp_cc_mdss_byte1_div_clk_src,

			&disp_cc_mdss_dp_link1_div_clk_src,

			&disp_cc_mdss_dp_link_div_clk_src,

		};

		unsigned int i;

		static bool offset_applied;



		/*

		 * note: trion == lucid, except for the prepare() op

		 * only apply the offsets once (in case of deferred probe)

		 */

		if (!offset_applied) {

			for (i = 0; i < ARRAY_SIZE(rcgs); i++)

				rcgs[i]->cmd_rcgr -= 4;



			for (i = 0; i < ARRAY_SIZE(divs); i++) {

				divs[i]->reg -= 4;

				divs[i]->width = 4;

			}



			disp_cc_mdss_ahb_clk.halt_reg -= 4;

			disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;



			offset_applied = true;

		}



		disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;



		disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c;

		disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;

		disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;

		disp_cc_pll0.vco_table = lucid_5lpe_vco;

		disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c;

		disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;

		disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;

		disp_cc_pll1.vco_table = lucid_5lpe_vco;

	}



	clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);