drm/i915: move and group gmbus members under display.gmbus (203eb5a9) · Commits · EulixOS / Software / Kernel

drivers/gpu/drm/i915/display/intel_cdclk.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -2098,12 +2098,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
		* functions use cdclk. Not all platforms/ports do,
		* but we'll lock them all for simplicity.
		*/
		mutex_lock(&dev_priv->gmbus_mutex);
		mutex_lock(&dev_priv->display.gmbus.mutex);
		for_each_intel_dp(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

		mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
		&dev_priv->gmbus_mutex);
		&dev_priv->display.gmbus.mutex);
		}

		intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
		@@ -2113,7 +2113,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,

		mutex_unlock(&intel_dp->aux.hw_mutex);
		}
		mutex_unlock(&dev_priv->gmbus_mutex);
		mutex_unlock(&dev_priv->display.gmbus.mutex);

		for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

drivers/gpu/drm/i915/display/intel_display_core.h

+23 −0

Original line number	Diff line number	Diff line
		@@ -6,7 +6,11 @@
		#ifndef __INTEL_DISPLAY_CORE_H__
		#define __INTEL_DISPLAY_CORE_H__

		#include <linux/mutex.h>
		#include <linux/types.h>
		#include <linux/wait.h>

		#include "intel_gmbus.h"

		struct drm_i915_private;
		struct intel_atomic_state;
		@@ -76,6 +80,25 @@ struct intel_display {
		/* Display internal color functions */
		const struct intel_color_funcs *color;
		} funcs;

		/* Grouping using anonymous structs. Keep sorted. */
		struct {
		/*
		* Base address of where the gmbus and gpio blocks are located
		* (either on PCH or on SoC for platforms without PCH).
		*/
		u32 mmio_base;

		/*
		* gmbus.mutex protects against concurrent usage of the single
		* hw gmbus controller on different i2c buses.
		*/
		struct mutex mutex;

		struct intel_gmbus *bus[GMBUS_NUM_PINS];

		wait_queue_head_t wait_queue;
		} gmbus;
		};

		#endif /* __INTEL_DISPLAY_CORE_H__ */

drivers/gpu/drm/i915/display/intel_dp_aux.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -42,7 +42,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
		bool done;

		#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
		done = wait_event_timeout(i915->gmbus_wait_queue, C,
		done = wait_event_timeout(i915->display.gmbus.wait_queue, C,
		msecs_to_jiffies_timeout(timeout_ms));

		/* just trace the final value */

drivers/gpu/drm/i915/display/intel_gmbus.c

+23 −23

Original line number	Diff line number	Diff line
		@@ -369,7 +369,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
		if (!has_gmbus_irq(dev_priv))
		irq_en = 0;

		add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
		add_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);
		intel_de_write_fw(dev_priv, GMBUS4, irq_en);

		status \|= GMBUS_SATOER;
		@@ -380,7 +380,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
		50);

		intel_de_write_fw(dev_priv, GMBUS4, 0);
		remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
		remove_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);

		if (gmbus2 & GMBUS_SATOER)
		return -ENXIO;
		@@ -400,7 +400,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
		if (has_gmbus_irq(dev_priv))
		irq_enable = GMBUS_IDLE_EN;

		add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
		add_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);
		intel_de_write_fw(dev_priv, GMBUS4, irq_enable);

		ret = intel_wait_for_register_fw(&dev_priv->uncore,
		@@ -408,7 +408,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
		10);

		intel_de_write_fw(dev_priv, GMBUS4, 0);
		remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
		remove_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);

		return ret;
		}
		@@ -791,7 +791,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
		int ret;

		wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
		mutex_lock(&dev_priv->gmbus_mutex);
		mutex_lock(&dev_priv->display.gmbus.mutex);

		/*
		* In order to output Aksv to the receiver, use an indexed write to
		@@ -800,7 +800,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
		*/
		ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);

		mutex_unlock(&dev_priv->gmbus_mutex);
		mutex_unlock(&dev_priv->display.gmbus.mutex);
		intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);

		return ret;
		@@ -826,7 +826,7 @@ static void gmbus_lock_bus(struct i2c_adapter *adapter,
		struct intel_gmbus *bus = to_intel_gmbus(adapter);
		struct drm_i915_private *dev_priv = bus->dev_priv;

		mutex_lock(&dev_priv->gmbus_mutex);
		mutex_lock(&dev_priv->display.gmbus.mutex);
		}

		static int gmbus_trylock_bus(struct i2c_adapter *adapter,
		@@ -835,7 +835,7 @@ static int gmbus_trylock_bus(struct i2c_adapter *adapter,
		struct intel_gmbus *bus = to_intel_gmbus(adapter);
		struct drm_i915_private *dev_priv = bus->dev_priv;

		return mutex_trylock(&dev_priv->gmbus_mutex);
		return mutex_trylock(&dev_priv->display.gmbus.mutex);
		}

		static void gmbus_unlock_bus(struct i2c_adapter *adapter,
		@@ -844,7 +844,7 @@ static void gmbus_unlock_bus(struct i2c_adapter *adapter,
		struct intel_gmbus *bus = to_intel_gmbus(adapter);
		struct drm_i915_private *dev_priv = bus->dev_priv;

		mutex_unlock(&dev_priv->gmbus_mutex);
		mutex_unlock(&dev_priv->display.gmbus.mutex);
		}

		static const struct i2c_lock_operations gmbus_lock_ops = {
		@@ -864,18 +864,18 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
		int ret;

		if (IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv))
		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
		dev_priv->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
		else if (!HAS_GMCH(dev_priv))
		/*
		* Broxton uses the same PCH offsets for South Display Engine,
		* even though it doesn't have a PCH.
		*/
		dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
		dev_priv->display.gmbus.mmio_base = PCH_DISPLAY_BASE;

		mutex_init(&dev_priv->gmbus_mutex);
		init_waitqueue_head(&dev_priv->gmbus_wait_queue);
		mutex_init(&dev_priv->display.gmbus.mutex);
		init_waitqueue_head(&dev_priv->display.gmbus.wait_queue);

		for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
		for (pin = 0; pin < ARRAY_SIZE(dev_priv->display.gmbus.bus); pin++) {
		const struct gmbus_pin *gmbus_pin;
		struct intel_gmbus *bus;

		@@ -922,7 +922,7 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
		goto err;
		}

		dev_priv->gmbus[pin] = bus;
		dev_priv->display.gmbus.bus[pin] = bus;
		}

		intel_gmbus_reset(dev_priv);
		@@ -938,11 +938,11 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
		struct i2c_adapter intel_gmbus_get_adapter(struct drm_i915_private dev_priv,
		unsigned int pin)
		{
		if (drm_WARN_ON(&dev_priv->drm, pin >= ARRAY_SIZE(dev_priv->gmbus) \|\|
		!dev_priv->gmbus[pin]))
		if (drm_WARN_ON(&dev_priv->drm, pin >= ARRAY_SIZE(dev_priv->display.gmbus.bus) \|\|
		!dev_priv->display.gmbus.bus[pin]))
		return NULL;

		return &dev_priv->gmbus[pin]->adapter;
		return &dev_priv->display.gmbus.bus[pin]->adapter;
		}

		void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
		@@ -950,7 +950,7 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
		struct intel_gmbus *bus = to_intel_gmbus(adapter);
		struct drm_i915_private *dev_priv = bus->dev_priv;

		mutex_lock(&dev_priv->gmbus_mutex);
		mutex_lock(&dev_priv->display.gmbus.mutex);

		bus->force_bit += force_bit ? 1 : -1;
		drm_dbg_kms(&dev_priv->drm,
		@@ -958,7 +958,7 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
		force_bit ? "en" : "dis", adapter->name,
		bus->force_bit);

		mutex_unlock(&dev_priv->gmbus_mutex);
		mutex_unlock(&dev_priv->display.gmbus.mutex);
		}

		bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
		@@ -972,16 +972,16 @@ void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
		{
		unsigned int pin;

		for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
		for (pin = 0; pin < ARRAY_SIZE(dev_priv->display.gmbus.bus); pin++) {
		struct intel_gmbus *bus;

		bus = dev_priv->gmbus[pin];
		bus = dev_priv->display.gmbus.bus[pin];
		if (!bus)
		continue;

		i2c_del_adapter(&bus->adapter);

		kfree(bus);
		dev_priv->gmbus[pin] = NULL;
		dev_priv->display.gmbus.bus[pin] = NULL;
		}
		}

drivers/gpu/drm/i915/i915_drv.h

+0 −16

Original line number	Diff line number	Diff line
		@@ -47,7 +47,6 @@
		#include "display/intel_fbc.h"
		#include "display/intel_frontbuffer.h"
		#include "display/intel_global_state.h"
		#include "display/intel_gmbus.h"
		#include "display/intel_opregion.h"

		#include "gem/i915_gem_context_types.h"
		@@ -89,7 +88,6 @@ struct intel_connector;
		struct intel_dp;
		struct intel_encoder;
		struct intel_fbdev;
		struct intel_gmbus;
		struct intel_limit;
		struct intel_overlay;
		struct intel_overlay_error_state;
		@@ -383,25 +381,11 @@ struct drm_i915_private {

		struct intel_dmc dmc;

		struct intel_gmbus *gmbus[GMBUS_NUM_PINS];

		/** gmbus_mutex protects against concurrent usage of the single hw gmbus
		* controller on different i2c buses. */
		struct mutex gmbus_mutex;

		/**
		* Base address of where the gmbus and gpio blocks are located (either
		* on PCH or on SoC for platforms without PCH).
		*/
		u32 gpio_mmio_base;

		/* MMIO base address for MIPI regs */
		u32 mipi_mmio_base;

		u32 pps_mmio_base;

		wait_queue_head_t gmbus_wait_queue;

		struct pci_dev *bridge_dev;

		struct rb_root uabi_engines;