Commit 203a1c3e authored by Andy Shevchenko's avatar Andy Shevchenko
Browse files

pinctrl: intel: Use same order of bit fields for PADCFG2 



PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same
for PADCFG2 bit fields. No functional changes intended.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
parent 346c8364

drivers/pinctrl/intel/pinctrl-intel.c

+1 −1
Original line number Diff line number Diff line
@@ -88,9 +88,9 @@ 
#define PADCFG1_TERM_800		(BIT(2) | BIT(1) | BIT(0))



#define PADCFG2				0x008

#define PADCFG2_DEBEN			BIT(0)

#define PADCFG2_DEBOUNCE_SHIFT		1

#define PADCFG2_DEBOUNCE_MASK		GENMASK(4, 1)

#define PADCFG2_DEBEN			BIT(0)



#define DEBOUNCE_PERIOD_NSEC		31250