Commit 20293269 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Remove ATC L2 access for MMHUB 2.1.x 



MMHUB 2.1.x versions don't have ATCL2. Remove accesses to ATCL2 registers.

Since they are non-existing registers, read access will cause a
'Completer Abort' and gets reported when AER is enabled with the below patch.
Tagging with the patch so that this is backported along with it.

v2: squash in uninitialized warning fix (Nathan Chancellor)

Fixes: 8795e182 ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()")

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent bb3c846a

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

+8 −20
Original line number Diff line number Diff line
@@ -32,8 +32,6 @@ 
#include "gc/gc_10_1_0_offset.h"

#include "soc15_common.h"



#define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid                      0x064d

#define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid_BASE_IDX             0

#define mmDAGB0_CNTL_MISC2_Sienna_Cichlid                       0x0070

#define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX              0
@@ -574,7 +572,6 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad 
	case IP_VERSION(2, 1, 0):

	case IP_VERSION(2, 1, 1):

	case IP_VERSION(2, 1, 2):

		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);

		def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);

		break;

	default:
@@ -608,8 +605,6 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad 
	case IP_VERSION(2, 1, 0):

	case IP_VERSION(2, 1, 1):

	case IP_VERSION(2, 1, 2):

		if (def != data)

			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);

		if (def1 != data1)

			WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1);

		break;
@@ -634,8 +629,8 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade 
	case IP_VERSION(2, 1, 0):

	case IP_VERSION(2, 1, 1):

	case IP_VERSION(2, 1, 2):

		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);

		break;

		/* There is no ATCL2 in MMHUB for 2.1.x */

		return;

	default:

		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);

		break;
@@ -646,18 +641,8 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade 
	else

		data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;



	if (def != data) {

		switch (adev->ip_versions[MMHUB_HWIP][0]) {

		case IP_VERSION(2, 1, 0):

		case IP_VERSION(2, 1, 1):

		case IP_VERSION(2, 1, 2):

			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);

			break;

		default:

	if (def != data)

		WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);

			break;

		}

	}

}



static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
@@ -695,7 +680,10 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 
	case IP_VERSION(2, 1, 0):

	case IP_VERSION(2, 1, 1):

	case IP_VERSION(2, 1, 2):

		data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);

		/* There is no ATCL2 in MMHUB for 2.1.x. Keep the status

		 * based on DAGB

		 */

		data = MM_ATC_L2_MISC_CG__ENABLE_MASK;

		data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);

		break;

	default: