Commit 1ff7bc3b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pm-5.19-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm 

Pull more power management updates from Rafael Wysocki:
 "These update the ARM cpufreq drivers and fix up the CPPC cpufreq
  driver after recent changes, update the OPP code and PM documentation
  and add power sequences support to the system reboot and power off
  code.

  Specifics:

   - Add Tegra234 cpufreq support (Sumit Gupta)

   - Clean up and enhance the Mediatek cpufreq driver (Wan Jiabing,
     Rex-BC Chen, and Jia-Wei Chang)

   - Fix up the CPPC cpufreq driver after recent changes (Zheng Bin,
     Pierre Gondois)

   - Minor update to dt-binding for Qcom's opp-v2-kryo-cpu (Yassine
     Oudjana)

   - Use list iterator only inside the list_for_each_entry loop
     (Xiaomeng Tong, and Jakob Koschel)

   - New APIs related to finding OPP based on interconnect bandwidth
     (Krzysztof Kozlowski)

   - Fix the missing of_node_put() in _bandwidth_supported() (Dan
     Carpenter)

   - Cleanups (Krzysztof Kozlowski, and Viresh Kumar)

   - Add Out of Band mode description to the intel-speed-select utility
     documentation (Srinivas Pandruvada)

   - Add power sequences support to the system reboot and power off code
     and make related platform-specific changes for multiple platforms
     (Dmitry Osipenko, Geert Uytterhoeven)"

* tag 'pm-5.19-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (60 commits)
  cpufreq: CPPC: Fix unused-function warning
  cpufreq: CPPC: Fix build error without CONFIG_ACPI_CPPC_CPUFREQ_FIE
  Documentation: admin-guide: PM: Add Out of Band mode
  kernel/reboot: Change registration order of legacy power-off handler
  m68k: virt: Switch to new sys-off handler API
  kernel/reboot: Add devm_register_restart_handler()
  kernel/reboot: Add devm_register_power_off_handler()
  soc/tegra: pmc: Use sys-off handler API to power off Nexus 7 properly
  reboot: Remove pm_power_off_prepare()
  regulator: pfuze100: Use devm_register_sys_off_handler()
  ACPI: power: Switch to sys-off handler API
  memory: emif: Use kernel_can_power_off()
  mips: Use do_kernel_power_off()
  ia64: Use do_kernel_power_off()
  x86: Use do_kernel_power_off()
  sh: Use do_kernel_power_off()
  m68k: Switch to new sys-off handler API
  powerpc: Use do_kernel_power_off()
  xen/x86: Use do_kernel_power_off()
  parisc: Use do_kernel_power_off()
  ...
parents 32665a9e 9f9c1f68

Documentation/admin-guide/pm/intel-speed-select.rst

+22 −0
Original line number Diff line number Diff line
@@ -262,6 +262,28 @@ Which shows that the base frequency now increased from 2600 MHz at performance 
level 0 to 2800 MHz at performance level 4. As a result, any workload, which can

use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.



Changing performance level via BMC Interface

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



It is possible to change SST-PP level using out of band (OOB) agent (Via some

remote management console, through BMC "Baseboard Management Controller"

interface). This mode is supported from the Sapphire Rapids processor

generation. The kernel and tool change to support this mode is added to Linux

kernel version 5.18. To enable this feature, kernel config

"CONFIG_INTEL_HFI_THERMAL" is required. The minimum version of the tool

is "v1.12" to support this feature, which is part of Linux kernel version 5.18.



To support such configuration, this tool can be used as a daemon. Add

a command line option --oob::



 # intel-speed-select --oob

 Intel(R) Speed Select Technology

 Executing on CPU model:143[0x8f]

 OOB mode is enabled and will run as daemon



In this mode the tool will online/offline CPUs based on the new performance

level.



Check presence of other Intel(R) SST features

---------------------------------------------

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml

0 → 100644
+52 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings



maintainers:

  - Sumit Gupta <sumitg@nvidia.com>

  - Mikko Perttunen <mperttunen@nvidia.com>

  - Jon Hunter <jonathanh@nvidia.com>

  - Thierry Reding <thierry.reding@gmail.com>



description: |+

  The Tegra CPU COMPLEX CLUSTER area contains memory-mapped

  registers that initiate CPU frequency/voltage transitions.



properties:

  $nodename:

    pattern: "ccplex@([0-9a-f]+)$"



  compatible:

    enum:

      - nvidia,tegra186-ccplex-cluster

      - nvidia,tegra234-ccplex-cluster



  reg:

    maxItems: 1



  nvidia,bpmp:

    $ref: '/schemas/types.yaml#/definitions/phandle'

    description: |

      Specifies the BPMP node that needs to be queried to get

      operating point data for all CPUs.



additionalProperties: false



required:

  - compatible

  - reg

  - nvidia,bpmp

  - status



examples:

  - |

    ccplex@e000000 {

      compatible = "nvidia,tegra234-ccplex-cluster";

      reg = <0x0e000000 0x5ffff>;

      nvidia,bpmp = <&bpmp>;

      status = "okay";

    };

Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt

+7 −0
Original line number Diff line number Diff line
@@ -20,6 +20,13 @@ Optional properties: 
	       Vsram to fit SoC specific needs. When absent, the voltage scaling

	       flow is handled by hardware, hence no software "voltage tracking" is

	       needed.

- mediatek,cci:

	Used to confirm the link status between cpufreq and mediatek cci. Because

	cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.

	To prevent the issue of high frequency and low voltage, we need to use this

	property to make sure mediatek cci is ready.

	For details of mediatek cci, please refer to

	Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml

- #cooling-cells:

	For details, please refer to

	Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml

Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml

+26 −30
Original line number Diff line number Diff line
@@ -17,10 +17,10 @@ description: | 
  the CPU frequencies subset and voltage value of each OPP varies based on

  the silicon variant in use.

  Qualcomm Technologies, Inc. Process Voltage Scaling Tables

  defines the voltage and frequency value based on the msm-id in SMEM

  and speedbin blown in the efuse combination.

  The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC

  to provide the OPP framework with required information (existing HW bitmap).

  defines the voltage and frequency value based on the speedbin blown in

  the efuse combination.

  The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide

  the OPP framework with required information (existing HW bitmap).

  This is used to determine the voltage and frequency value for each OPP of

  operating-points-v2 table when it is parsed by the OPP framework.
@@ -50,15 +50,11 @@ patternProperties: 
        description: |

          A single 32 bit bitmap value, representing compatible HW.

          Bitmap:

          0:  MSM8996 V3, speedbin 0

          1:  MSM8996 V3, speedbin 1

          2:  MSM8996 V3, speedbin 2

          3:  unused

          4:  MSM8996 SG, speedbin 0

          5:  MSM8996 SG, speedbin 1

          6:  MSM8996 SG, speedbin 2

          7-31:  unused

        maximum: 0x77

          0:  MSM8996, speedbin 0

          1:  MSM8996, speedbin 1

          2:  MSM8996, speedbin 2

          3-31:  unused

        maximum: 0x7



      clock-latency-ns: true
@@ -184,19 +180,19 @@ examples: 
            opp-307200000 {

                opp-hz = /bits/ 64 <307200000>;

                opp-microvolt = <905000 905000 1140000>;

                opp-supported-hw = <0x77>;

                opp-supported-hw = <0x7>;

                clock-latency-ns = <200000>;

            };

            opp-1593600000 {

                opp-hz = /bits/ 64 <1593600000>;

            opp-1401600000 {

                opp-hz = /bits/ 64 <1401600000>;

                opp-microvolt = <1140000 905000 1140000>;

                opp-supported-hw = <0x71>;

                opp-supported-hw = <0x5>;

                clock-latency-ns = <200000>;

            };

            opp-2188800000 {

                opp-hz = /bits/ 64 <2188800000>;

            opp-1593600000 {

                opp-hz = /bits/ 64 <1593600000>;

                opp-microvolt = <1140000 905000 1140000>;

                opp-supported-hw = <0x10>;

                opp-supported-hw = <0x1>;

                clock-latency-ns = <200000>;

            };

        };
@@ -209,25 +205,25 @@ examples: 
            opp-307200000 {

                opp-hz = /bits/ 64 <307200000>;

                opp-microvolt = <905000 905000 1140000>;

                opp-supported-hw = <0x77>;

                opp-supported-hw = <0x7>;

                clock-latency-ns = <200000>;

            };

            opp-1593600000 {

                opp-hz = /bits/ 64 <1593600000>;

            opp-1804800000 {

                opp-hz = /bits/ 64 <1804800000>;

                opp-microvolt = <1140000 905000 1140000>;

                opp-supported-hw = <0x70>;

                opp-supported-hw = <0x6>;

                clock-latency-ns = <200000>;

            };

            opp-2150400000 {

                opp-hz = /bits/ 64 <2150400000>;

            opp-1900800000 {

                opp-hz = /bits/ 64 <1900800000>;

                opp-microvolt = <1140000 905000 1140000>;

                opp-supported-hw = <0x31>;

                opp-supported-hw = <0x4>;

                clock-latency-ns = <200000>;

            };

            opp-2342400000 {

                opp-hz = /bits/ 64 <2342400000>;

            opp-2150400000 {

                opp-hz = /bits/ 64 <2150400000>;

                opp-microvolt = <1140000 905000 1140000>;

                opp-supported-hw = <0x10>;

                opp-supported-hw = <0x1>;

                clock-latency-ns = <200000>;

            };

        };

arch/arm/kernel/reboot.c

+1 −3
Original line number Diff line number Diff line
@@ -116,9 +116,7 @@ void machine_power_off(void) 
{

	local_irq_disable();

	smp_send_stop();



	if (pm_power_off)

		pm_power_off();

	do_kernel_power_off();

}



/*