Commit 1fd02f66 authored by Julia Lawall's avatar Julia Lawall Committed by Michael Ellerman
Browse files

powerpc: fix typos in comments 



Various spelling mistakes in comments.
Detected with the help of Coccinelle.

Signed-off-by: default avatarJulia Lawall <Julia.Lawall@inria.fr>
Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220430185654.5855-1-Julia.Lawall@inria.fr
parent c14d31ba

arch/powerpc/boot/cuboot-hotfoot.c

+1 −1
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ static void hotfoot_fixups(void) 


		printf("Fixing devtree for 4M Flash\n");

		

		/* First fix up the base addresse */

		/* First fix up the base address */

		getprop(devp, "reg", regs, sizeof(regs));

		regs[0] = 0;

		regs[1] = 0xffc00000;

arch/powerpc/crypto/aes-spe-glue.c

+1 −1
Original line number Diff line number Diff line
@@ -404,7 +404,7 @@ static int ppc_xts_decrypt(struct skcipher_request *req) 


/*

 * Algorithm definitions. Disabling alignment (cra_alignmask=0) was chosen

 * because the e500 platform can handle unaligned reads/writes very efficently.

 * because the e500 platform can handle unaligned reads/writes very efficiently.

 * This improves IPsec thoughput by another few percent. Additionally we assume

 * that AES context is always aligned to at least 8 bytes because it is created

 * with kmalloc() in the crypto infrastructure

arch/powerpc/kernel/cputable.c

+1 −1
Original line number Diff line number Diff line
@@ -2025,7 +2025,7 @@ static struct cpu_spec * __init setup_cpu_spec(unsigned long offset, 
		 * oprofile_cpu_type already has a value, then we are

		 * possibly overriding a real PVR with a logical one,

		 * and, in that case, keep the current value for

		 * oprofile_cpu_type. Futhermore, let's ensure that the

		 * oprofile_cpu_type. Furthermore, let's ensure that the

		 * fix for the PMAO bug is enabled on compatibility mode.

		 */

		if (old.oprofile_cpu_type != NULL) {

arch/powerpc/kernel/dawr.c

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ int set_dawr(int nr, struct arch_hw_breakpoint *brk) 
	dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) >> 3;

	/*

	 * DAWR length is stored in field MDR bits 48:53.  Matches range in

	 * doublewords (64 bits) baised by -1 eg. 0b000000=1DW and

	 * doublewords (64 bits) biased by -1 eg. 0b000000=1DW and

	 * 0b111111=64DW.

	 * brk->hw_len is in bytes.

	 * This aligns up to double word size, shifts and does the bias.

arch/powerpc/kernel/eeh.c

+2 −2
Original line number Diff line number Diff line
@@ -1329,7 +1329,7 @@ int eeh_pe_set_option(struct eeh_pe *pe, int option) 


	/*

	 * EEH functionality could possibly be disabled, just

	 * return error for the case. And the EEH functinality

	 * return error for the case. And the EEH functionality

	 * isn't expected to be disabled on one specific PE.

	 */

	switch (option) {
@@ -1804,7 +1804,7 @@ static int eeh_debugfs_break_device(struct pci_dev *pdev) 
	 *    PE freeze. Using the in_8() accessor skips the eeh detection hook

	 *    so the freeze hook so the EEH Detection machinery won't be

	 *    triggered here. This is to match the usual behaviour of EEH

	 *    where the HW will asyncronously freeze a PE and it's up to

	 *    where the HW will asynchronously freeze a PE and it's up to

	 *    the kernel to notice and deal with it.

	 *

	 * 3. Turn Memory space back on. This is more important for VFs