Commit 1fc31638 authored Sep 27, 2021 by Bing Guo Committed by Alex Deucher Nov 03, 2021

drm/amd/display: Fix bpc calculation for specific encodings



[Why]
1. YCbCr 4:2:2 8bpc/10bpc modes are blocked for HDMI by policy
2. A YCbCr 4:2:0 calculation error blocked some 4:2:0 timing modes

[How]
YCbCr 4:2:2 8bpc/10bpc modes are allowed for HDMI
Fix YCbCr 4:2:0 calculation error

Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Bing Guo <Bing.Guo@amd.com>
Reviewed-by: Chris Park <chris.park@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent bca5bea4

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

+3 −10

Original line number	Diff line number	Diff line
		@@ -3576,16 +3576,9 @@ static double TruncToValidBPP(
		MinDSCBPP = 8;
		MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16;
		} else {
		if (Output == dm_hdmi) {
		NonDSCBPP0 = 24;
		NonDSCBPP1 = 24;
		NonDSCBPP2 = 24;
		}
		else {
		NonDSCBPP0 = 16;
		NonDSCBPP1 = 20;
		NonDSCBPP2 = 24;
		}

		if (Format == dm_n422) {
		MinDSCBPP = 7;

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

+5 −9

Original line number	Diff line number	Diff line
		@@ -3892,15 +3892,11 @@ static double TruncToValidBPP(
		MinDSCBPP = 8;
		MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16;
		} else {
		if (Output == dm_hdmi) {
		NonDSCBPP0 = 24;
		NonDSCBPP1 = 24;
		NonDSCBPP2 = 24;
		} else {

		NonDSCBPP0 = 16;
		NonDSCBPP1 = 20;
		NonDSCBPP2 = 24;
		}

		if (Format == dm_n422) {
		MinDSCBPP = 7;
		MaxDSCBPP = 2 * DSCInputBitPerComponent - 1.0 / 16.0;