Commit 1fb7a9fb authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g044: Add GPT clock and reset entry 



Add GPT clock and reset entry to CPG driver.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220510110653.7326-2-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent f2906aa8

drivers/clk/renesas/r9a07g044-cpg.c

+4 −1
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ static const struct { 
};



static const struct {

	struct rzg2l_mod_clk common[71];

	struct rzg2l_mod_clk common[72];

#ifdef CONFIG_CLK_R9A07G054

	struct rzg2l_mod_clk drp[0];

#endif
@@ -204,6 +204,8 @@ static const struct { 
					0x534, 1),

		DEF_MOD("ostm2_pclk",	R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,

					0x534, 2),

		DEF_MOD("gpt_pclk",	R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,

					0x540, 0),

		DEF_MOD("wdt0_pclk",	R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,

					0x548, 0),

		DEF_MOD("wdt0_clk",	R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
@@ -346,6 +348,7 @@ static struct rzg2l_reset r9a07g044_resets[] = { 
	DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),

	DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),

	DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),

	DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),

	DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),

	DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),

	DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),