Commit 1f928f51 authored by Oak Zeng's avatar Oak Zeng Committed by Alex Deucher
Browse files

drm/amdgpu: Use physical translation mode to access page table 



On A+A platform, CPU write page directory and page table in cached
mode. So it is necessary for page table walker to snoop CPU cache.
This setting is necessary for page walker to snoop page directory
and page table data out of CPU cache.

Signed-off-by: default avatarOak Zeng <Oak.Zeng@amd.com>
Acked-by: default avatarChristian Konig <christian.koenig@amd.com>
Reviewed-by: default avatarFelix Kuehling <felix.kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 35d5f224

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+7 −2
Original line number Diff line number Diff line
@@ -173,8 +173,13 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);



	tmp = mmVM_L2_CNTL4_DEFAULT;

	if (adev->gmc.xgmi.connected_to_cpu) {

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);

	} else {

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

	}

	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);

}

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

+11 −2
Original line number Diff line number Diff line
@@ -178,8 +178,17 @@ static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev) 
	WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp);



	tmp = regVM_L2_CNTL4_DEFAULT;

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

	if (adev->gmc.xgmi.connected_to_cpu) {

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

				    VMC_TAP_PDE_REQUEST_PHYSICAL, 1);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

				    VMC_TAP_PTE_REQUEST_PHYSICAL, 1);

	} else {

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

				    VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

				    VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

	}

	WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp);

}