Commit 1f625659 authored by Mukul Joshi's avatar Mukul Joshi Committed by Alex Deucher
Browse files

drm/amdgpu: Query correct register for DF hashing on Aldebaran 



For Aldebaran, driver needs to query DramMegaBaseAddress to
check if DF hashing is enabled.

Signed-off-by: default avatarMukul Joshi <mukul.joshi@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHarish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 295c4f51

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

+5 −4
Original line number Diff line number Diff line
@@ -277,13 +277,14 @@ static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev) 
{

	u32 tmp;



	tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);

	if (adev->asic_type == CHIP_ALDEBARAN)

	if (adev->asic_type == CHIP_ALDEBARAN) {

		tmp = RREG32_SOC15(DF, 0, mmDF_GCM_AON0_DramMegaBaseAddress0);

		tmp &=

		ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;

	else

	} else {

		tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);

		tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;



	}

	tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;



	return tmp;

drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h

+3 −0
Original line number Diff line number Diff line
@@ -33,6 +33,9 @@ 
#define mmDF_CS_UMC_AON0_DramBaseAddress0								0x0044

#define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX							0



#define mmDF_GCM_AON0_DramMegaBaseAddress0								0x0064

#define mmDF_GCM_AON0_DramMegaBaseAddress0_BASE_IDX							0



#define smnPerfMonCtlLo0					0x01d440UL

#define smnPerfMonCtlHi0					0x01d444UL

#define smnPerfMonCtlLo1					0x01d450UL