Loading arch/arm/include/asm/hardware/iop_adma.h +0 −2 Original line number Diff line number Diff line Loading @@ -49,7 +49,6 @@ struct iop_adma_device { /** * struct iop_adma_chan - internal representation of an ADMA device * @pending: allows batching of hardware operations * @completed_cookie: identifier for the most recently completed operation * @lock: serializes enqueue/dequeue operations to the slot pool * @mmr_base: memory mapped register base * @chain: device chain view of the descriptors Loading @@ -62,7 +61,6 @@ struct iop_adma_device { */ struct iop_adma_chan { int pending; dma_cookie_t completed_cookie; spinlock_t lock; /* protects the descriptor slot pool */ void __iomem *mmr_base; struct list_head chain; Loading drivers/dma/amba-pl08x.c +11 −27 Original line number Diff line number Diff line Loading @@ -85,6 +85,8 @@ #include <linux/slab.h> #include <asm/hardware/pl080.h> #include "dmaengine.h" #define DRIVER_NAME "pl08xdmac" static struct amba_driver pl08x_amba_driver; Loading Loading @@ -919,13 +921,10 @@ static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx) struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan); struct pl08x_txd *txd = to_pl08x_txd(tx); unsigned long flags; dma_cookie_t cookie; spin_lock_irqsave(&plchan->lock, flags); plchan->chan.cookie += 1; if (plchan->chan.cookie < 0) plchan->chan.cookie = 1; tx->cookie = plchan->chan.cookie; cookie = dma_cookie_assign(tx); /* Put this onto the pending list */ list_add_tail(&txd->node, &plchan->pend_list); Loading @@ -945,7 +944,7 @@ static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx) spin_unlock_irqrestore(&plchan->lock, flags); return tx->cookie; return cookie; } static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( Loading @@ -965,31 +964,17 @@ static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); dma_cookie_t last_used; dma_cookie_t last_complete; enum dma_status ret; u32 bytesleft = 0; last_used = plchan->chan.cookie; last_complete = plchan->lc; ret = dma_async_is_complete(cookie, last_complete, last_used); if (ret == DMA_SUCCESS) { dma_set_tx_state(txstate, last_complete, last_used, 0); ret = dma_cookie_status(chan, cookie, txstate); if (ret == DMA_SUCCESS) return ret; } /* * This cookie not complete yet * Get number of bytes left in the active transactions and queue */ last_used = plchan->chan.cookie; last_complete = plchan->lc; /* Get number of bytes left in the active transactions and queue */ bytesleft = pl08x_getbytes_chan(plchan); dma_set_tx_state(txstate, last_complete, last_used, bytesleft); dma_set_residue(txstate, pl08x_getbytes_chan(plchan)); if (plchan->state == PL08X_CHAN_PAUSED) return DMA_PAUSED; Loading Loading @@ -1543,7 +1528,7 @@ static void pl08x_tasklet(unsigned long data) if (txd) { /* Update last completed */ plchan->lc = txd->tx.cookie; dma_cookie_complete(&txd->tx); } /* If a new descriptor is queued, set it up plchan->at is NULL here */ Loading Loading @@ -1724,8 +1709,7 @@ static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, chan->name); chan->chan.device = dmadev; chan->chan.cookie = 0; chan->lc = 0; dma_cookie_init(&chan->chan); spin_lock_init(&chan->lock); INIT_LIST_HEAD(&chan->pend_list); Loading drivers/dma/at_hdmac.c +11 −37 Original line number Diff line number Diff line Loading @@ -27,6 +27,7 @@ #include <linux/of_device.h> #include "at_hdmac_regs.h" #include "dmaengine.h" /* * Glossary Loading Loading @@ -191,27 +192,6 @@ static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, *prev = desc; } /** * atc_assign_cookie - compute and assign new cookie * @atchan: channel we work on * @desc: descriptor to assign cookie for * * Called with atchan->lock held and bh disabled */ static dma_cookie_t atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc) { dma_cookie_t cookie = atchan->chan_common.cookie; if (++cookie < 0) cookie = 1; atchan->chan_common.cookie = cookie; desc->txd.cookie = cookie; return cookie; } /** * atc_dostart - starts the DMA engine for real * @atchan: the channel we want to start Loading Loading @@ -269,7 +249,7 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) dev_vdbg(chan2dev(&atchan->chan_common), "descriptor %u complete\n", txd->cookie); atchan->completed_cookie = txd->cookie; dma_cookie_complete(txd); /* move children to free_list */ list_splice_init(&desc->tx_list, &atchan->free_list); Loading Loading @@ -547,7 +527,7 @@ static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) unsigned long flags; spin_lock_irqsave(&atchan->lock, flags); cookie = atc_assign_cookie(atchan, desc); cookie = dma_cookie_assign(tx); if (list_empty(&atchan->active_list)) { dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", Loading Loading @@ -1016,26 +996,20 @@ atc_tx_status(struct dma_chan *chan, spin_lock_irqsave(&atchan->lock, flags); last_complete = atchan->completed_cookie; last_used = chan->cookie; ret = dma_async_is_complete(cookie, last_complete, last_used); ret = dma_cookie_status(chan, cookie, txstate); if (ret != DMA_SUCCESS) { atc_cleanup_descriptors(atchan); last_complete = atchan->completed_cookie; last_used = chan->cookie; ret = dma_async_is_complete(cookie, last_complete, last_used); ret = dma_cookie_status(chan, cookie, txstate); } last_complete = chan->completed_cookie; last_used = chan->cookie; spin_unlock_irqrestore(&atchan->lock, flags); if (ret != DMA_SUCCESS) dma_set_tx_state(txstate, last_complete, last_used, atc_first_active(atchan)->len); else dma_set_tx_state(txstate, last_complete, last_used, 0); dma_set_residue(txstate, atc_first_active(atchan)->len); if (atc_chan_is_paused(atchan)) ret = DMA_PAUSED; Loading Loading @@ -1129,7 +1103,7 @@ static int atc_alloc_chan_resources(struct dma_chan *chan) spin_lock_irqsave(&atchan->lock, flags); atchan->descs_allocated = i; list_splice(&tmp_list, &atchan->free_list); atchan->completed_cookie = chan->cookie = 1; dma_cookie_init(chan); spin_unlock_irqrestore(&atchan->lock, flags); /* channel parameters */ Loading Loading @@ -1329,7 +1303,7 @@ static int __init at_dma_probe(struct platform_device *pdev) struct at_dma_chan *atchan = &atdma->chan[i]; atchan->chan_common.device = &atdma->dma_common; atchan->chan_common.cookie = atchan->completed_cookie = 1; dma_cookie_init(&atchan->chan_common); list_add_tail(&atchan->chan_common.device_node, &atdma->dma_common.channels); Loading drivers/dma/at_hdmac_regs.h +0 −2 Original line number Diff line number Diff line Loading @@ -208,7 +208,6 @@ enum atc_status { * @save_dscr: for cyclic operations, preserve next descriptor address in * the cyclic list on suspend/resume cycle * @lock: serializes enqueue/dequeue operations to descriptors lists * @completed_cookie: identifier for the most recently completed operation * @active_list: list of descriptors dmaengine is being running on * @queue: list of descriptors ready to be submitted to engine * @free_list: list of descriptors usable by the channel Loading @@ -227,7 +226,6 @@ struct at_dma_chan { spinlock_t lock; /* these other elements are all protected by lock */ dma_cookie_t completed_cookie; struct list_head active_list; struct list_head queue; struct list_head free_list; Loading drivers/dma/coh901318.c +10 −29 Original line number Diff line number Diff line Loading @@ -24,6 +24,7 @@ #include <mach/coh901318.h> #include "coh901318_lli.h" #include "dmaengine.h" #define COHC_2_DEV(cohc) (&cohc->chan.dev->device) Loading Loading @@ -59,7 +60,6 @@ struct coh901318_base { struct coh901318_chan { spinlock_t lock; int allocated; int completed; int id; int stopped; Loading Loading @@ -318,20 +318,6 @@ static int coh901318_prep_linked_list(struct coh901318_chan *cohc, return 0; } static dma_cookie_t coh901318_assign_cookie(struct coh901318_chan *cohc, struct coh901318_desc *cohd) { dma_cookie_t cookie = cohc->chan.cookie; if (++cookie < 0) cookie = 1; cohc->chan.cookie = cookie; cohd->desc.cookie = cookie; return cookie; } static struct coh901318_desc * coh901318_desc_get(struct coh901318_chan *cohc) Loading Loading @@ -705,7 +691,7 @@ static void dma_tasklet(unsigned long data) callback_param = cohd_fin->desc.callback_param; /* sign this job as completed on the channel */ cohc->completed = cohd_fin->desc.cookie; dma_cookie_complete(&cohd_fin->desc); /* release the lli allocation and remove the descriptor */ coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli); Loading Loading @@ -929,7 +915,7 @@ static int coh901318_alloc_chan_resources(struct dma_chan *chan) coh901318_config(cohc, NULL); cohc->allocated = 1; cohc->completed = chan->cookie = 1; dma_cookie_init(chan); spin_unlock_irqrestore(&cohc->lock, flags); Loading Loading @@ -966,16 +952,16 @@ coh901318_tx_submit(struct dma_async_tx_descriptor *tx) desc); struct coh901318_chan *cohc = to_coh901318_chan(tx->chan); unsigned long flags; dma_cookie_t cookie; spin_lock_irqsave(&cohc->lock, flags); tx->cookie = coh901318_assign_cookie(cohc, cohd); cookie = dma_cookie_assign(tx); coh901318_desc_queue(cohc, cohd); spin_unlock_irqrestore(&cohc->lock, flags); return tx->cookie; return cookie; } static struct dma_async_tx_descriptor * Loading Loading @@ -1165,17 +1151,12 @@ coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { struct coh901318_chan *cohc = to_coh901318_chan(chan); dma_cookie_t last_used; dma_cookie_t last_complete; int ret; last_complete = cohc->completed; last_used = chan->cookie; enum dma_status ret; ret = dma_async_is_complete(cookie, last_complete, last_used); ret = dma_cookie_status(chan, cookie, txstate); /* FIXME: should be conditional on ret != DMA_SUCCESS? */ dma_set_residue(txstate, coh901318_get_bytes_left(chan)); dma_set_tx_state(txstate, last_complete, last_used, coh901318_get_bytes_left(chan)); if (ret == DMA_IN_PROGRESS && cohc->stopped) ret = DMA_PAUSED; Loading Loading
arch/arm/include/asm/hardware/iop_adma.h +0 −2 Original line number Diff line number Diff line Loading @@ -49,7 +49,6 @@ struct iop_adma_device { /** * struct iop_adma_chan - internal representation of an ADMA device * @pending: allows batching of hardware operations * @completed_cookie: identifier for the most recently completed operation * @lock: serializes enqueue/dequeue operations to the slot pool * @mmr_base: memory mapped register base * @chain: device chain view of the descriptors Loading @@ -62,7 +61,6 @@ struct iop_adma_device { */ struct iop_adma_chan { int pending; dma_cookie_t completed_cookie; spinlock_t lock; /* protects the descriptor slot pool */ void __iomem *mmr_base; struct list_head chain; Loading
drivers/dma/amba-pl08x.c +11 −27 Original line number Diff line number Diff line Loading @@ -85,6 +85,8 @@ #include <linux/slab.h> #include <asm/hardware/pl080.h> #include "dmaengine.h" #define DRIVER_NAME "pl08xdmac" static struct amba_driver pl08x_amba_driver; Loading Loading @@ -919,13 +921,10 @@ static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx) struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan); struct pl08x_txd *txd = to_pl08x_txd(tx); unsigned long flags; dma_cookie_t cookie; spin_lock_irqsave(&plchan->lock, flags); plchan->chan.cookie += 1; if (plchan->chan.cookie < 0) plchan->chan.cookie = 1; tx->cookie = plchan->chan.cookie; cookie = dma_cookie_assign(tx); /* Put this onto the pending list */ list_add_tail(&txd->node, &plchan->pend_list); Loading @@ -945,7 +944,7 @@ static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx) spin_unlock_irqrestore(&plchan->lock, flags); return tx->cookie; return cookie; } static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( Loading @@ -965,31 +964,17 @@ static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); dma_cookie_t last_used; dma_cookie_t last_complete; enum dma_status ret; u32 bytesleft = 0; last_used = plchan->chan.cookie; last_complete = plchan->lc; ret = dma_async_is_complete(cookie, last_complete, last_used); if (ret == DMA_SUCCESS) { dma_set_tx_state(txstate, last_complete, last_used, 0); ret = dma_cookie_status(chan, cookie, txstate); if (ret == DMA_SUCCESS) return ret; } /* * This cookie not complete yet * Get number of bytes left in the active transactions and queue */ last_used = plchan->chan.cookie; last_complete = plchan->lc; /* Get number of bytes left in the active transactions and queue */ bytesleft = pl08x_getbytes_chan(plchan); dma_set_tx_state(txstate, last_complete, last_used, bytesleft); dma_set_residue(txstate, pl08x_getbytes_chan(plchan)); if (plchan->state == PL08X_CHAN_PAUSED) return DMA_PAUSED; Loading Loading @@ -1543,7 +1528,7 @@ static void pl08x_tasklet(unsigned long data) if (txd) { /* Update last completed */ plchan->lc = txd->tx.cookie; dma_cookie_complete(&txd->tx); } /* If a new descriptor is queued, set it up plchan->at is NULL here */ Loading Loading @@ -1724,8 +1709,7 @@ static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, chan->name); chan->chan.device = dmadev; chan->chan.cookie = 0; chan->lc = 0; dma_cookie_init(&chan->chan); spin_lock_init(&chan->lock); INIT_LIST_HEAD(&chan->pend_list); Loading
drivers/dma/at_hdmac.c +11 −37 Original line number Diff line number Diff line Loading @@ -27,6 +27,7 @@ #include <linux/of_device.h> #include "at_hdmac_regs.h" #include "dmaengine.h" /* * Glossary Loading Loading @@ -191,27 +192,6 @@ static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, *prev = desc; } /** * atc_assign_cookie - compute and assign new cookie * @atchan: channel we work on * @desc: descriptor to assign cookie for * * Called with atchan->lock held and bh disabled */ static dma_cookie_t atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc) { dma_cookie_t cookie = atchan->chan_common.cookie; if (++cookie < 0) cookie = 1; atchan->chan_common.cookie = cookie; desc->txd.cookie = cookie; return cookie; } /** * atc_dostart - starts the DMA engine for real * @atchan: the channel we want to start Loading Loading @@ -269,7 +249,7 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) dev_vdbg(chan2dev(&atchan->chan_common), "descriptor %u complete\n", txd->cookie); atchan->completed_cookie = txd->cookie; dma_cookie_complete(txd); /* move children to free_list */ list_splice_init(&desc->tx_list, &atchan->free_list); Loading Loading @@ -547,7 +527,7 @@ static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) unsigned long flags; spin_lock_irqsave(&atchan->lock, flags); cookie = atc_assign_cookie(atchan, desc); cookie = dma_cookie_assign(tx); if (list_empty(&atchan->active_list)) { dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", Loading Loading @@ -1016,26 +996,20 @@ atc_tx_status(struct dma_chan *chan, spin_lock_irqsave(&atchan->lock, flags); last_complete = atchan->completed_cookie; last_used = chan->cookie; ret = dma_async_is_complete(cookie, last_complete, last_used); ret = dma_cookie_status(chan, cookie, txstate); if (ret != DMA_SUCCESS) { atc_cleanup_descriptors(atchan); last_complete = atchan->completed_cookie; last_used = chan->cookie; ret = dma_async_is_complete(cookie, last_complete, last_used); ret = dma_cookie_status(chan, cookie, txstate); } last_complete = chan->completed_cookie; last_used = chan->cookie; spin_unlock_irqrestore(&atchan->lock, flags); if (ret != DMA_SUCCESS) dma_set_tx_state(txstate, last_complete, last_used, atc_first_active(atchan)->len); else dma_set_tx_state(txstate, last_complete, last_used, 0); dma_set_residue(txstate, atc_first_active(atchan)->len); if (atc_chan_is_paused(atchan)) ret = DMA_PAUSED; Loading Loading @@ -1129,7 +1103,7 @@ static int atc_alloc_chan_resources(struct dma_chan *chan) spin_lock_irqsave(&atchan->lock, flags); atchan->descs_allocated = i; list_splice(&tmp_list, &atchan->free_list); atchan->completed_cookie = chan->cookie = 1; dma_cookie_init(chan); spin_unlock_irqrestore(&atchan->lock, flags); /* channel parameters */ Loading Loading @@ -1329,7 +1303,7 @@ static int __init at_dma_probe(struct platform_device *pdev) struct at_dma_chan *atchan = &atdma->chan[i]; atchan->chan_common.device = &atdma->dma_common; atchan->chan_common.cookie = atchan->completed_cookie = 1; dma_cookie_init(&atchan->chan_common); list_add_tail(&atchan->chan_common.device_node, &atdma->dma_common.channels); Loading
drivers/dma/at_hdmac_regs.h +0 −2 Original line number Diff line number Diff line Loading @@ -208,7 +208,6 @@ enum atc_status { * @save_dscr: for cyclic operations, preserve next descriptor address in * the cyclic list on suspend/resume cycle * @lock: serializes enqueue/dequeue operations to descriptors lists * @completed_cookie: identifier for the most recently completed operation * @active_list: list of descriptors dmaengine is being running on * @queue: list of descriptors ready to be submitted to engine * @free_list: list of descriptors usable by the channel Loading @@ -227,7 +226,6 @@ struct at_dma_chan { spinlock_t lock; /* these other elements are all protected by lock */ dma_cookie_t completed_cookie; struct list_head active_list; struct list_head queue; struct list_head free_list; Loading
drivers/dma/coh901318.c +10 −29 Original line number Diff line number Diff line Loading @@ -24,6 +24,7 @@ #include <mach/coh901318.h> #include "coh901318_lli.h" #include "dmaengine.h" #define COHC_2_DEV(cohc) (&cohc->chan.dev->device) Loading Loading @@ -59,7 +60,6 @@ struct coh901318_base { struct coh901318_chan { spinlock_t lock; int allocated; int completed; int id; int stopped; Loading Loading @@ -318,20 +318,6 @@ static int coh901318_prep_linked_list(struct coh901318_chan *cohc, return 0; } static dma_cookie_t coh901318_assign_cookie(struct coh901318_chan *cohc, struct coh901318_desc *cohd) { dma_cookie_t cookie = cohc->chan.cookie; if (++cookie < 0) cookie = 1; cohc->chan.cookie = cookie; cohd->desc.cookie = cookie; return cookie; } static struct coh901318_desc * coh901318_desc_get(struct coh901318_chan *cohc) Loading Loading @@ -705,7 +691,7 @@ static void dma_tasklet(unsigned long data) callback_param = cohd_fin->desc.callback_param; /* sign this job as completed on the channel */ cohc->completed = cohd_fin->desc.cookie; dma_cookie_complete(&cohd_fin->desc); /* release the lli allocation and remove the descriptor */ coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli); Loading Loading @@ -929,7 +915,7 @@ static int coh901318_alloc_chan_resources(struct dma_chan *chan) coh901318_config(cohc, NULL); cohc->allocated = 1; cohc->completed = chan->cookie = 1; dma_cookie_init(chan); spin_unlock_irqrestore(&cohc->lock, flags); Loading Loading @@ -966,16 +952,16 @@ coh901318_tx_submit(struct dma_async_tx_descriptor *tx) desc); struct coh901318_chan *cohc = to_coh901318_chan(tx->chan); unsigned long flags; dma_cookie_t cookie; spin_lock_irqsave(&cohc->lock, flags); tx->cookie = coh901318_assign_cookie(cohc, cohd); cookie = dma_cookie_assign(tx); coh901318_desc_queue(cohc, cohd); spin_unlock_irqrestore(&cohc->lock, flags); return tx->cookie; return cookie; } static struct dma_async_tx_descriptor * Loading Loading @@ -1165,17 +1151,12 @@ coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { struct coh901318_chan *cohc = to_coh901318_chan(chan); dma_cookie_t last_used; dma_cookie_t last_complete; int ret; last_complete = cohc->completed; last_used = chan->cookie; enum dma_status ret; ret = dma_async_is_complete(cookie, last_complete, last_used); ret = dma_cookie_status(chan, cookie, txstate); /* FIXME: should be conditional on ret != DMA_SUCCESS? */ dma_set_residue(txstate, coh901318_get_bytes_left(chan)); dma_set_tx_state(txstate, last_complete, last_used, coh901318_get_bytes_left(chan)); if (ret == DMA_IN_PROGRESS && cohc->stopped) ret = DMA_PAUSED; Loading