Commit 1f1b20f1 authored by Jes Sorensen's avatar Jes Sorensen Committed by Kalle Valo
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rtl8xxxu: Do queue init in same order as 8723bu vendor driver 



Reorganize the init sequence in order to be able to compare to the
8723bu vendor driver's init sequence.

Signed-off-by: default avatarJes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent f30ed675

drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

+37 −31
Original line number Diff line number Diff line
@@ -6017,32 +6017,6 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) 
			val8 &= 0xf8;

			rtl8xxxu_write8(priv, 0xa3, val8);

		}



		if (priv->ep_tx_normal_queue)

			val8 = TX_PAGE_NUM_NORM_PQ;

		else

			val8 = 0;



		rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);



		val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;



		if (priv->ep_tx_high_queue)

			val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);

		if (priv->ep_tx_low_queue)

			val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);



		rtl8xxxu_write32(priv, REG_RQPN, val32);



		/*

		 * Set TX buffer boundary

		 */

		val8 = TX_TOTAL_PAGE_NUM + 1;

		rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);

		rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);

		rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);

		rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);

		rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);

	}



	ret = rtl8xxxu_download_firmware(priv);
@@ -6054,11 +6028,6 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) 
	if (ret)

		goto exit;



	ret = rtl8xxxu_init_queue_priority(priv);

	dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);

	if (ret)

		goto exit;



	/* Fix USB interface interference issue */

	if (priv->rtlchip == 0x8723a) {

		rtl8xxxu_write8(priv, 0xfe40, 0xe0);
@@ -6158,6 +6127,43 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) 
		rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);

	}



	if (!macpower){

		if (priv->ep_tx_normal_queue)

			val8 = TX_PAGE_NUM_NORM_PQ;

		else

			val8 = 0;



		rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);



		val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;



		if (priv->ep_tx_high_queue)

			val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);

		if (priv->ep_tx_low_queue)

			val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);



		rtl8xxxu_write32(priv, REG_RQPN, val32);



		/*

		 * Set TX buffer boundary

		 */

		val8 = TX_TOTAL_PAGE_NUM + 1;



		if (priv->rtlchip == 0x8723b)

			val8 -= 1;



		rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);

		rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);

		rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);

		rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);

		rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);

	}



	ret = rtl8xxxu_init_queue_priority(priv);

	dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);

	if (ret)

		goto exit;



	/* RFSW Control - clear bit 14 ?? */

	rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);

	/* 0x07000760 */