Commit 1f123163 authored by Athira Rajeev's avatar Athira Rajeev Committed by Michael Ellerman
Browse files

powerpc/perf: Fix to update generic event codes for power10 



Fix the event code for events: branch-instructions (to PM_BR_FIN),
branch-misses (to PM_MPRED_BR_FIN) and cache-misses (to
PM_LD_DEMAND_MISS_L1_FIN) for power10 PMU. Update the
list of generic events with this modified event code.

Signed-off-by: default avatarAthira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1606409684-1589-6-git-send-email-atrajeev@linux.vnet.ibm.com
parent c0e39857

arch/powerpc/perf/power10-events-list.h

+3 −0
Original line number Diff line number Diff line
@@ -15,6 +15,9 @@ EVENT(PM_EXEC_STALL, 0x30008); 
EVENT(PM_RUN_INST_CMPL,				0x500fa);

EVENT(PM_BR_CMPL,                               0x4d05e);

EVENT(PM_BR_MPRED_CMPL,                         0x400f6);

EVENT(PM_BR_FIN,				0x2f04a);

EVENT(PM_MPRED_BR_FIN,				0x3e098);

EVENT(PM_LD_DEMAND_MISS_L1_FIN,			0x400f0);



/* All L1 D cache load references counted at finish, gated by reject */

EVENT(PM_LD_REF_L1,				0x100fc);

arch/powerpc/perf/power10-pmu.c

+9 −6
Original line number Diff line number Diff line
@@ -114,6 +114,9 @@ GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 
GENERIC_EVENT_ATTR(cache-misses,		PM_LD_MISS_L1);

GENERIC_EVENT_ATTR(mem-loads,			MEM_LOADS);

GENERIC_EVENT_ATTR(mem-stores,			MEM_STORES);

GENERIC_EVENT_ATTR(branch-instructions,		PM_BR_FIN);

GENERIC_EVENT_ATTR(branch-misses,		PM_MPRED_BR_FIN);

GENERIC_EVENT_ATTR(cache-misses,		PM_LD_DEMAND_MISS_L1_FIN);



CACHE_EVENT_ATTR(L1-dcache-load-misses,		PM_LD_MISS_L1);

CACHE_EVENT_ATTR(L1-dcache-loads,		PM_LD_REF_L1);
@@ -157,10 +160,10 @@ static struct attribute *power10_events_attr_dd1[] = { 
static struct attribute *power10_events_attr[] = {

	GENERIC_EVENT_PTR(PM_RUN_CYC),

	GENERIC_EVENT_PTR(PM_RUN_INST_CMPL),

	GENERIC_EVENT_PTR(PM_BR_CMPL),

	GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),

	GENERIC_EVENT_PTR(PM_BR_FIN),

	GENERIC_EVENT_PTR(PM_MPRED_BR_FIN),

	GENERIC_EVENT_PTR(PM_LD_REF_L1),

	GENERIC_EVENT_PTR(PM_LD_MISS_L1),

	GENERIC_EVENT_PTR(PM_LD_DEMAND_MISS_L1_FIN),

	GENERIC_EVENT_PTR(MEM_LOADS),

	GENERIC_EVENT_PTR(MEM_STORES),

	CACHE_EVENT_PTR(PM_LD_MISS_L1),
@@ -259,10 +262,10 @@ static int power10_generic_events_dd1[] = { 
static int power10_generic_events[] = {

	[PERF_COUNT_HW_CPU_CYCLES] =			PM_RUN_CYC,

	[PERF_COUNT_HW_INSTRUCTIONS] =			PM_RUN_INST_CMPL,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =		PM_BR_CMPL,

	[PERF_COUNT_HW_BRANCH_MISSES] =			PM_BR_MPRED_CMPL,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =		PM_BR_FIN,

	[PERF_COUNT_HW_BRANCH_MISSES] =			PM_MPRED_BR_FIN,

	[PERF_COUNT_HW_CACHE_REFERENCES] =		PM_LD_REF_L1,

	[PERF_COUNT_HW_CACHE_MISSES] =			PM_LD_MISS_L1,

	[PERF_COUNT_HW_CACHE_MISSES] =			PM_LD_DEMAND_MISS_L1_FIN,

};



static u64 power10_bhrb_filter_map(u64 branch_sample_type)