Unverified Commit 1eac2820 authored Feb 08, 2023 by Heiko Stuebner Committed by Palmer Dabbelt Feb 21, 2023

RISC-V: fix ordering of Zbb extension



As Andrew reported,
    Zb* comes after Zi* according 27.11 "Subset Naming Convention"
so fix the ordering accordingly.

Reported-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230208225328.1636017-2-heiko@sntech.de


Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

parent 9ddfc3cd

arch/riscv/kernel/cpu.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -185,9 +185,9 @@ arch_initcall(riscv_cpuinfo_init);
		* New entries to this struct should follow the ordering rules described above.
		*/
		static struct riscv_isa_ext_data isa_ext_arr[] = {
		__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
		__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
		__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
		__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
		__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
		__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
		__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),