Commit 1e9a5f52 authored by devi priya's avatar devi priya Committed by Wen Zhiwei
Browse files

clk: qcom: ipq9574: Update the alpha PLL type for GPLLs 

stable inclusion
from stable-v6.6.51
commit eaccebe663b2513ae4ea306617caa0680b233400
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IAYRVR

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=eaccebe663b2513ae4ea306617caa0680b233400



--------------------------------

[ Upstream commit 6357efe3abead68048729adf11a9363881657939 ]

Update PLL offsets to DEFAULT_EVO to configure MDIO to 800MHz.

The incorrect clock frequency leads to an incorrect MDIO clock. This,
in turn, affects the MDIO hardware configurations as the divider is
calculated from the MDIO clock frequency. If the clock frequency is
not as expected, the MDIO register fails due to the generation of an
incorrect MDIO frequency.

This issue is critical as it results in incorrect MDIO configurations
and ultimately leads to the MDIO function not working. This results in
a complete feature failure affecting all Ethernet PHYs. Specifically,
Ethernet will not work on IPQ9574 due to this issue.

Currently, the clock frequency is set to CLK_ALPHA_PLL_TYPE_DEFAULT.
However, this setting does not yield the expected clock frequency.
To rectify this, we need to change this to CLK_ALPHA_PLL_TYPE_DEFAULT_EVO.

This modification ensures that the clock frequency aligns with our
expectations, thereby resolving the MDIO register failure and ensuring
the proper functioning of the Ethernet on IPQ9574.

Fixes: d75b82cf ("clk: qcom: Add Global Clock Controller driver for IPQ9574")
Signed-off-by: default avatardevi priya <quic_devipriy@quicinc.com>
Signed-off-by: default avatarAmandeep Singh <quic_amansing@quicinc.com>
Link: https://lore.kernel.org/r/20240806061105.2849944-1-quic_amansing@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarWen Zhiwei <wenzhiwei@kylinos.cn>
parent 53ade208

drivers/clk/qcom/gcc-ipq9574.c

+6 −6
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ static const struct clk_parent_data gcc_sleep_clk_data[] = { 


static struct clk_alpha_pll gpll0_main = {

	.offset = 0x20000,

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],

	.clkr = {

		.enable_reg = 0x0b000,

		.enable_mask = BIT(0),
@@ -93,7 +93,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { 


static struct clk_alpha_pll_postdiv gpll0 = {

	.offset = 0x20000,

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],

	.width = 4,

	.clkr.hw.init = &(const struct clk_init_data) {

		.name = "gpll0",
@@ -107,7 +107,7 @@ static struct clk_alpha_pll_postdiv gpll0 = { 


static struct clk_alpha_pll gpll4_main = {

	.offset = 0x22000,

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],

	.clkr = {

		.enable_reg = 0x0b000,

		.enable_mask = BIT(2),
@@ -122,7 +122,7 @@ static struct clk_alpha_pll gpll4_main = { 


static struct clk_alpha_pll_postdiv gpll4 = {

	.offset = 0x22000,

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],

	.width = 4,

	.clkr.hw.init = &(const struct clk_init_data) {

		.name = "gpll4",
@@ -136,7 +136,7 @@ static struct clk_alpha_pll_postdiv gpll4 = { 


static struct clk_alpha_pll gpll2_main = {

	.offset = 0x21000,

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],

	.clkr = {

		.enable_reg = 0x0b000,

		.enable_mask = BIT(1),
@@ -151,7 +151,7 @@ static struct clk_alpha_pll gpll2_main = { 


static struct clk_alpha_pll_postdiv gpll2 = {

	.offset = 0x21000,

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],

	.width = 4,

	.clkr.hw.init = &(const struct clk_init_data) {

		.name = "gpll2",