Commit 1e827785 authored by Sricharan R's avatar Sricharan R Committed by Bjorn Andersson
Browse files

arm64: dts: Add ipq6018 SoC and CP01 board support 



Add initial device tree support for the Qualcomm IPQ6018 SoC and
CP01 evaluation board.

Co-developed-by: default avatarAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: default avatarAbhishek Sahu <absahu@codeaurora.org>
Co-developed-by: default avatarSivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: default avatarSivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: default avatarSricharan R <sricharan@codeaurora.org>
Link: https://lore.kernel.org/r/1579439601-14810-5-git-send-email-sricharan@codeaurora.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 2f0c17fa

arch/arm64/boot/dts/qcom/Makefile

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@@ -2,6 +2,7 @@ 
dtb-$(CONFIG_ARCH_QCOM)	+= apq8016-sbc.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-db820c.dtb

dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-mtp.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-longcheer-l8150.dtb

arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts

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+30 −0
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 * IPQ6018 CP01 board device tree source

 *

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



/dts-v1/;



#include "ipq6018.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";

	compatible = "qcom,ipq6018-cp01", "qcom,ipq6018";



	aliases {

		serial0 = &blsp1_uart3;

	};



	chosen {

		stdout-path = "serial0:115200n8";

		bootargs-append = " swiotlb=1";

	};

};



&blsp1_uart3 {

	pinctrl-0 = <&serial_3_pins>;

	pinctrl-names = "default";

	status = "ok";

};

arch/arm64/boot/dts/qcom/ipq6018.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 * IPQ6018 SoC device tree source

 *

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-ipq6018.h>



/ {

	#address-cells = <2>;

	#size-cells = <2>;

	interrupt-parent = <&intc>;



	clocks {

		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			clock-frequency = <32000>;

			#clock-cells = <0>;

		};



		xo: xo {

			compatible = "fixed-clock";

			clock-frequency = <24000000>;

			#clock-cells = <0>;

		};

	};



	cpus: cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x1>;

			next-level-cache = <&L2_0>;

		};



		CPU2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x2>;

			next-level-cache = <&L2_0>;

		};



		CPU3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x3>;

			next-level-cache = <&L2_0>;

		};



		L2_0: l2-cache {

			compatible = "cache";

			cache-level = <0x2>;

		};

	};



	pmuv8: pmu {

		compatible = "arm,cortex-a53-pmu";

		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |

					 IRQ_TYPE_LEVEL_HIGH)>;

	};



	psci: psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		tz: tz@48500000 {

			reg = <0x0 0x48500000 0x0 0x00200000>;

			no-map;

		};

	};



	soc: soc {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0 0xffffffff>;

		dma-ranges;

		compatible = "simple-bus";



		tlmm: pinctrl@1000000 {

			compatible = "qcom,ipq6018-pinctrl";

			reg = <0x01000000 0x300000>;

			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&tlmm 0 80>;

			interrupt-controller;

			#interrupt-cells = <2>;



			serial_3_pins: serial3-pinmux {

				pins = "gpio44", "gpio45";

				function = "blsp2_uart";

				drive-strength = <8>;

				bias-pull-down;

			};

		};



		gcc: gcc@1800000 {

			compatible = "qcom,gcc-ipq6018";

			reg = <0x01800000 0x80000>;

			clocks = <&xo>, <&sleep_clk>;

			clock-names = "xo", "sleep_clk";

			#clock-cells = <1>;

			#reset-cells = <1>;

		};



		blsp1_uart3: serial@78b1000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x078b1000 0x200>;

			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,

				<&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

		};



		intc: interrupt-controller@b000000 {

			compatible = "qcom,msm-qgic2";

			interrupt-controller;

			#interrupt-cells = <0x3>;

			reg =   <0x0b000000 0x1000>,  /*GICD*/

				<0x0b002000 0x1000>,  /*GICC*/

				<0x0b001000 0x1000>,  /*GICH*/

				<0x0b004000 0x1000>;  /*GICV*/

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		timer {

			compatible = "arm,armv8-timer";

			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		};



		timer@b120000 {

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			compatible = "arm,armv7-timer-mem";

			reg = <0x0b120000 0x1000>;

			clock-frequency = <19200000>;



			frame@b120000 {

				frame-number = <0>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b121000 0x1000>,

				      <0x0b122000 0x1000>;

			};



			frame@b123000 {

				frame-number = <1>;

				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb123000 0x1000>;

				status = "disabled";

			};



			frame@b124000 {

				frame-number = <2>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b124000 0x1000>;

				status = "disabled";

			};



			frame@b125000 {

				frame-number = <3>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b125000 0x1000>;

				status = "disabled";

			};



			frame@b126000 {

				frame-number = <4>;

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b126000 0x1000>;

				status = "disabled";

			};



			frame@b127000 {

				frame-number = <5>;

				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b127000 0x1000>;

				status = "disabled";

			};



			frame@b128000 {

				frame-number = <6>;

				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b128000 0x1000>;

				status = "disabled";

			};

		};



	};

};