Commit 1e56ebc9 authored by Wolfram Sang's avatar Wolfram Sang Committed by Geert Uytterhoeven
Browse files

clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks 



Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220726210110.1444-2-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 32fb5425

drivers/clk/renesas/r8a779f0-cpg-mssr.c

+10 −0
Original line number Diff line number Diff line
@@ -108,6 +108,11 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { 
	DEF_FIXED("cbfusa",	R8A779F0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cpex",	R8A779F0_CLK_CPEX,	CLK_EXTAL,	2, 1),



	DEF_FIXED("sasyncrt",	R8A779F0_CLK_SASYNCRT,	CLK_PLL5_DIV4,	48, 1),

	DEF_FIXED("sasyncperd1", R8A779F0_CLK_SASYNCPERD1, CLK_PLL5_DIV4, 3, 1),

	DEF_FIXED("sasyncperd2", R8A779F0_CLK_SASYNCPERD2, R8A779F0_CLK_SASYNCPERD1, 2, 1),

	DEF_FIXED("sasyncperd4", R8A779F0_CLK_SASYNCPERD4, R8A779F0_CLK_SASYNCPERD1, 4, 1),



	DEF_GEN4_SDH("sdh0",	R8A779F0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SD("sd0",	R8A779F0_CLK_SD0,	R8A779F0_CLK_SD0H, 0x870),
@@ -140,6 +145,11 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 
	DEF_MOD("sdhi0",        706,    R8A779F0_CLK_SD0),

	DEF_MOD("sys-dmac0",	709,	R8A779F0_CLK_S0D3_PER),

	DEF_MOD("sys-dmac1",	710,	R8A779F0_CLK_S0D3_PER),

	DEF_MOD("tmu0",		713,	R8A779F0_CLK_SASYNCRT),

	DEF_MOD("tmu1",		714,	R8A779F0_CLK_SASYNCPERD2),

	DEF_MOD("tmu2",		715,	R8A779F0_CLK_SASYNCPERD2),

	DEF_MOD("tmu3",		716,	R8A779F0_CLK_SASYNCPERD2),

	DEF_MOD("tmu4",		717,	R8A779F0_CLK_SASYNCPERD2),

	DEF_MOD("wdt",		907,	R8A779F0_CLK_R),

	DEF_MOD("cmt0",		910,	R8A779F0_CLK_R),

	DEF_MOD("cmt1",		911,	R8A779F0_CLK_R),