Commit 1e41b3fe authored by Pavel Belous's avatar Pavel Belous Committed by David S. Miller
Browse files

net: atlantic: add support for 64-bit reads/writes 



This patch adds support for 64-bit reads/writes where applicable, e.g.
A2 supports them.

Signed-off-by: default avatarPavel Belous <pbelous@marvell.com>
Signed-off-by: default avatarMark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: default avatarIgor Russkikh <irusskikh@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 8bd60710

drivers/net/ethernet/aquantia/atlantic/aq_hw.h

+1 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ struct aq_hw_caps_s { 
	u8 rx_rings;

	bool flow_control;

	bool is_64_dma;

	bool op64bit;

	u32 priv_data_len;

};

drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c

+24 −5
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * aQuantia Corporation Network Driver

 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved

/* Atlantic Network Driver

 *

 * Copyright (C) 2014-2019 aQuantia Corporation

 * Copyright (C) 2019-2020 Marvell International Ltd.

 */



/* File aq_hw_utils.c: Definitions of helper functions used across
@@ -9,6 +10,9 @@ 
 */



#include "aq_hw_utils.h"



#include <linux/io-64-nonatomic-lo-hi.h>



#include "aq_hw.h"

#include "aq_nic.h"
@@ -56,13 +60,28 @@ void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value) 
 */

u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg)

{

	u64 value = aq_hw_read_reg(hw, reg);

	u64 value = U64_MAX;



	value |= (u64)aq_hw_read_reg(hw, reg + 4) << 32;

	if (hw->aq_nic_cfg->aq_hw_caps->op64bit)

		value = readq(hw->mmio + reg);

	else

		value = lo_hi_readq(hw->mmio + reg);



	if (value == U64_MAX &&

	    readl(hw->mmio + hw->aq_nic_cfg->aq_hw_caps->hw_alive_check_addr) == U32_MAX)

		aq_utils_obj_set(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG);



	return value;

}



void aq_hw_write_reg64(struct aq_hw_s *hw, u32 reg, u64 value)

{

	if (hw->aq_nic_cfg->aq_hw_caps->op64bit)

		writeq(value, hw->mmio + reg);

	else

		lo_hi_writeq(value, hw->mmio + reg);

}



int aq_hw_err_from_flags(struct aq_hw_s *hw)

{

	int err = 0;

drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h

+5 −3
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * aQuantia Corporation Network Driver

 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved

/* Atlantic Network Driver

 *

 * Copyright (C) 2014-2019 aQuantia Corporation

 * Copyright (C) 2019-2020 Marvell International Ltd.

 */



/* File aq_hw_utils.h: Declaration of helper functions used across hardware
@@ -33,6 +34,7 @@ u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift); 
u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg);

void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value);

u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg);

void aq_hw_write_reg64(struct aq_hw_s *hw, u32 reg, u64 value);

int aq_hw_err_from_flags(struct aq_hw_s *hw);

int aq_hw_num_tcs(struct aq_hw_s *hw);

int aq_hw_q_per_tc(struct aq_hw_s *hw);

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 


#define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \

	.is_64_dma = true,		  \

	.op64bit = false,		  \

	.msix_irqs = 4U,		  \

	.irq_mask = ~0U,		  \

	.vecs = HW_ATL_A0_RSS_MAX,	  \

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 


#define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \

	.is_64_dma = true,		  \

	.op64bit = false,		  \

	.msix_irqs = 8U,		  \

	.irq_mask = ~0U,		  \

	.vecs = HW_ATL_B0_RSS_MAX,	  \