Commit 1e34064b authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-fixes-5.17-2' of...

Merge tag 'irqchip-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull irqchip fixes from Marc Zyngier:

 - Don't register a hotplug notifier on GICv3 systems that advertise
   LPI support, but have no ITS to make use of it

 - Add missing DT matching for the thead,c900-plic variant of the
   SiFive PLIC

Link: https://lore.kernel.org/r/20220211110038.1179155-1-maz@kernel.org
parents dd7f5a11 1d4df649
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+15 −6
Original line number Diff line number Diff line
@@ -35,6 +35,10 @@ description:
  contains a specific memory layout, which is documented in chapter 8 of the
  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.

  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
  T-HEAD PLIC implementation requires setting a delegation bit to allow access
  from S-mode. So add thead,c900-plic to distinguish them.

maintainers:
  - Sagar Kadam <sagar.kadam@sifive.com>
  - Paul Walmsley  <paul.walmsley@sifive.com>
@@ -42,12 +46,17 @@ maintainers:

properties:
  compatible:
    items:
    oneOf:
      - items:
          - enum:
              - sifive,fu540-c000-plic
              - starfive,jh7100-plic
              - canaan,k210-plic
          - const: sifive,plic-1.0.0
      - items:
          - enum:
              - allwinner,sun20i-d1-plic
          - const: thead,c900-plic

  reg:
    maxItems: 1
+3 −0
Original line number Diff line number Diff line
@@ -5517,6 +5517,9 @@ int __init its_lpi_memreserve_init(void)
	if (!efi_enabled(EFI_CONFIG_TABLES))
		return 0;

	if (list_empty(&its_nodes))
		return 0;

	gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
	state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
				  "irqchip/arm/gicv3/memreserve:online",
+1 −0
Original line number Diff line number Diff line
@@ -398,3 +398,4 @@ static int __init plic_init(struct device_node *node,

IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */