Commit 1e1e73ee authored by David S. Miller's avatar David S. Miller
Browse files

Merge tag 'mlx5-fixes-2021-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux 



mlx5-fixes-2021-03-10

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 8373a0fe 84076c4c

drivers/infiniband/hw/mlx5/qp.c

+14 −4
Original line number Diff line number Diff line
@@ -1078,7 +1078,7 @@ static int _create_kernel_qp(struct mlx5_ib_dev *dev, 


	qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);

	MLX5_SET(qpc, qpc, uar_page, uar_index);

	MLX5_SET(qpc, qpc, ts_format, MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT);

	MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev));

	MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);



	/* Set "fast registration enabled" for all kernel QPs */
@@ -1188,7 +1188,8 @@ static int get_rq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 
		}

		return MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING;

	}

	return MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT;

	return fr_supported ? MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING :

			      MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT;

}



static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq)
@@ -1206,7 +1207,8 @@ static int get_sq_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq) 
		}

		return MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING;

	}

	return MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT;

	return fr_supported ? MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING :

			      MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT;

}



static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq,
@@ -1217,7 +1219,8 @@ static int get_qp_ts_format(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *send_cq, 
			MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING ||

		MLX5_CAP_ROCE(dev->mdev, qp_ts_format) ==

			MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME;

	int ts_format = MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;

	int ts_format = fr_supported ? MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :

				       MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;



	if (recv_cq &&

	    recv_cq->create_flags & IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)
@@ -1930,6 +1933,7 @@ static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 
	if (qp->flags & IB_QP_CREATE_MANAGED_RECV)

		MLX5_SET(qpc, qpc, cd_slave_receive, 1);



	MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev));

	MLX5_SET(qpc, qpc, rq_type, MLX5_SRQ_RQ);

	MLX5_SET(qpc, qpc, no_sq, 1);

	MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
@@ -4873,6 +4877,7 @@ static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 
	struct mlx5_ib_dev *dev;

	int has_net_offloads;

	__be64 *rq_pas0;

	int ts_format;

	void *in;

	void *rqc;

	void *wq;
@@ -4881,6 +4886,10 @@ static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 


	dev = to_mdev(pd->device);



	ts_format = get_rq_ts_format(dev, to_mcq(init_attr->cq));

	if (ts_format < 0)

		return ts_format;



	inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;

	in = kvzalloc(inlen, GFP_KERNEL);

	if (!in)
@@ -4890,6 +4899,7 @@ static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 
	rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);

	MLX5_SET(rqc,  rqc, mem_rq_type,

		 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);

	MLX5_SET(rqc, rqc, ts_format, ts_format);

	MLX5_SET(rqc, rqc, user_index, rwq->user_index);

	MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);

	MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);

drivers/net/ethernet/mellanox/mlx5/core/en.h

+4 −3
Original line number Diff line number Diff line
@@ -92,14 +92,15 @@ struct page_pool; 
				    MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)

#define MLX5_MPWRQ_PAGES_PER_WQE		BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)



#define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)

#define MLX5_ALIGN_MTTS(mtts)		(ALIGN(mtts, 8))

#define MLX5_ALIGNED_MTTS_OCTW(mtts)	((mtts) / 2)

#define MLX5_MTT_OCTW(mtts)		(MLX5_ALIGNED_MTTS_OCTW(MLX5_ALIGN_MTTS(mtts)))

/* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between

 * WQEs, This page will absorb write overflow by the hardware, when

 * receiving packets larger than MTU. These oversize packets are

 * dropped by the driver at a later stage.

 */

#define MLX5E_REQUIRED_WQE_MTTS		(ALIGN(MLX5_MPWRQ_PAGES_PER_WQE + 1, 8))

#define MLX5E_LOG_ALIGNED_MPWQE_PPW	(ilog2(MLX5E_REQUIRED_WQE_MTTS))

#define MLX5E_REQUIRED_WQE_MTTS		(MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1))

#define MLX5E_REQUIRED_MTTS(wqes)	(wqes * MLX5E_REQUIRED_WQE_MTTS)

#define MLX5E_MAX_RQ_NUM_MTTS	\

	((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */

drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c

+4 −4
Original line number Diff line number Diff line
@@ -685,14 +685,14 @@ int mlx5e_tc_tun_route_lookup(struct mlx5e_priv *priv, 
	u16 vport_num;

	int err = 0;



	if (flow_attr->ip_version == 4) {

	if (flow_attr->tun_ip_version == 4) {

		/* Addresses are swapped for decap */

		attr.fl.fl4.saddr = esw_attr->rx_tun_attr->dst_ip.v4;

		attr.fl.fl4.daddr = esw_attr->rx_tun_attr->src_ip.v4;

		err = mlx5e_route_lookup_ipv4_get(priv, priv->netdev, &attr);

	}

#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)

	else if (flow_attr->ip_version == 6) {

	else if (flow_attr->tun_ip_version == 6) {

		/* Addresses are swapped for decap */

		attr.fl.fl6.saddr = esw_attr->rx_tun_attr->dst_ip.v6;

		attr.fl.fl6.daddr = esw_attr->rx_tun_attr->src_ip.v6;
@@ -718,10 +718,10 @@ int mlx5e_tc_tun_route_lookup(struct mlx5e_priv *priv, 
	esw_attr->rx_tun_attr->decap_vport = vport_num;



out:

	if (flow_attr->ip_version == 4)

	if (flow_attr->tun_ip_version == 4)

		mlx5e_route_lookup_ipv4_put(&attr);

#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)

	else if (flow_attr->ip_version == 6)

	else if (flow_attr->tun_ip_version == 6)

		mlx5e_route_lookup_ipv6_put(&attr);

#endif

	return err;

drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c

+2 −1
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ int mlx5e_tc_set_attr_rx_tun(struct mlx5e_tc_flow *flow, 
	 * required to establish routing.

	 */

	flow_flag_set(flow, TUN_RX);

	flow->attr->tun_ip_version = ip_version;

	return 0;

}
@@ -1091,7 +1092,7 @@ int mlx5e_attach_decap_route(struct mlx5e_priv *priv, 
	if (err || !esw_attr->rx_tun_attr->decap_vport)

		goto out;



	key.ip_version = attr->ip_version;

	key.ip_version = attr->tun_ip_version;

	if (key.ip_version == 4)

		key.endpoint_ip.v4 = esw_attr->rx_tun_attr->dst_ip.v4;

	else

drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c

+4 −0
Original line number Diff line number Diff line
@@ -227,6 +227,10 @@ static int mlx5e_tc_tun_parse_geneve_options(struct mlx5e_priv *priv, 
	option_key = (struct geneve_opt *)&enc_opts.key->data[0];

	option_mask = (struct geneve_opt *)&enc_opts.mask->data[0];



	if (option_mask->opt_class == 0 && option_mask->type == 0 &&

	    !memchr_inv(option_mask->opt_data, 0, option_mask->length * 4))

		return 0;



	if (option_key->length > max_tlv_option_data_len) {

		NL_SET_ERR_MSG_MOD(extack,

				   "Matching on GENEVE options: unsupported option len");