Unverified Commit 1dc53232 authored by Mark Brown's avatar Mark Brown
Browse files

ADD SOF support for rembrandt platform 

Merge series from V sujith kumar Reddy <Vsujithkumar.Reddy@amd.com>:

This series consists of

1.Make ACP core code generic for newer SOC transition
2.Add support for Rembrandt plaform
3.Adding amd HS functionality to the sof core
4.increase SRAM inbox and outbox size to 1024
parents 2ca8c73b 40d3c041

include/sound/sof/dai.h

+2 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ enum sof_ipc_dai_type { 
	SOF_DAI_AMD_BT,			/**< AMD ACP BT*/

	SOF_DAI_AMD_SP,			/**< AMD ACP SP */

	SOF_DAI_AMD_DMIC,		/**< AMD ACP DMIC */

	SOF_DAI_AMD_HS,			/**< Amd HS */

	SOF_DAI_MEDIATEK_AFE,		/**< Mediatek AFE */

};
@@ -112,6 +113,7 @@ struct sof_ipc_dai_config { 
		struct sof_ipc_dai_acp_params acpbt;

		struct sof_ipc_dai_acp_params acpsp;

		struct sof_ipc_dai_acpdmic_params acpdmic;

		struct sof_ipc_dai_acp_params acphs;

		struct sof_ipc_dai_mtk_afe_params afe;

	};

} __packed;

sound/soc/sof/amd/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -31,4 +31,14 @@ config SND_SOC_SOF_AMD_RENOIR 
	select SND_SOC_SOF_AMD_COMMON

	help

	  Select this option for SOF support on AMD Renoir platform



config SND_SOC_SOF_AMD_REMBRANDT

	tristate "SOF support for REMBRANDT"

	depends on SND_SOC_SOF_PCI

	select SND_SOC_SOF_AMD_COMMON

	help

	  Select this option for SOF support on AMD Rembrandt platform

	  Say Y if you want to enable SOF on Rembrandt.

	  If unsure select "N".



endif

sound/soc/sof/amd/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -4,8 +4,10 @@ 
#

# Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.



snd-sof-amd-acp-objs := acp.o acp-loader.o acp-ipc.o acp-pcm.o acp-stream.o acp-trace.o

snd-sof-amd-acp-objs := acp.o acp-loader.o acp-ipc.o acp-pcm.o acp-stream.o acp-trace.o acp-common.o

snd-sof-amd-renoir-objs := pci-rn.o renoir.o

snd-sof-amd-rembrandt-objs := pci-rmb.o rembrandt.o



obj-$(CONFIG_SND_SOC_SOF_AMD_COMMON) += snd-sof-amd-acp.o

obj-$(CONFIG_SND_SOC_SOF_AMD_RENOIR) +=snd-sof-amd-renoir.o

obj-$(CONFIG_SND_SOC_SOF_AMD_REMBRANDT) +=snd-sof-amd-rembrandt.o

sound/soc/sof/amd/acp-common.c

0 → 100644
+111 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)

//

// This file is provided under a dual BSD/GPLv2 license. When using or

// redistributing this file, you may do so under either license.

//

// Copyright(c) 2022 Advanced Micro Devices, Inc.

//

// Authors: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>

//	    V sujith kumar Reddy <Vsujithkumar.Reddy@amd.com>



/* ACP-specific Common code */



#include "../sof-priv.h"

#include "../sof-audio.h"

#include "../ops.h"

#include "../sof-audio.h"

#include "acp.h"

#include "acp-dsp-offset.h"



int acp_dai_probe(struct snd_soc_dai *dai)

{

	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(dai->component);

	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);

	unsigned int val;



	val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->i2s_pin_config_offset);

	if (val != desc->i2s_mode) {

		dev_err(sdev->dev, "I2S Mode is not supported (I2S_PIN_CONFIG: %#x)\n", val);

		return -EINVAL;

	}



	return 0;

}

EXPORT_SYMBOL_NS(acp_dai_probe, SND_SOC_SOF_AMD_COMMON);



struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev)

{

	struct snd_sof_pdata *sof_pdata = sdev->pdata;

	const struct sof_dev_desc *desc = sof_pdata->desc;

	struct snd_soc_acpi_mach *mach;



	mach = snd_soc_acpi_find_machine(desc->machines);

	if (!mach) {

		dev_warn(sdev->dev, "No matching ASoC machine driver found\n");

		return NULL;

	}



	sof_pdata->tplg_filename = mach->sof_tplg_filename;

	sof_pdata->fw_filename = mach->fw_filename;



	return mach;

}



/* AMD Common DSP ops */

struct snd_sof_dsp_ops sof_acp_common_ops = {

	/* probe and remove */

	.probe			= amd_sof_acp_probe,

	.remove			= amd_sof_acp_remove,



	/* Register IO */

	.write			= sof_io_write,

	.read			= sof_io_read,



	/* Block IO */

	.block_read		= acp_dsp_block_read,

	.block_write		= acp_dsp_block_write,



	/*Firmware loading */

	.load_firmware		= snd_sof_load_firmware_memcpy,

	.pre_fw_run		= acp_dsp_pre_fw_run,

	.get_bar_index		= acp_get_bar_index,



	/* DSP core boot */

	.run			= acp_sof_dsp_run,



	/*IPC */

	.send_msg		= acp_sof_ipc_send_msg,

	.ipc_msg_data		= acp_sof_ipc_msg_data,

	.get_mailbox_offset	= acp_sof_ipc_get_mailbox_offset,

	.get_window_offset      = acp_sof_ipc_get_window_offset,

	.irq_thread		= acp_sof_ipc_irq_thread,



	/* stream callbacks */

	.pcm_open		= acp_pcm_open,

	.pcm_close		= acp_pcm_close,

	.pcm_hw_params		= acp_pcm_hw_params,



	.hw_info		= SNDRV_PCM_INFO_MMAP |

				  SNDRV_PCM_INFO_MMAP_VALID |

				  SNDRV_PCM_INFO_INTERLEAVED |

				  SNDRV_PCM_INFO_PAUSE |

				  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,



	/* Machine driver callbacks */

	.machine_select		= amd_sof_machine_select,

	.machine_register	= sof_machine_register,

	.machine_unregister	= sof_machine_unregister,



	/* Trace Logger */

	.trace_init		= acp_sof_trace_init,

	.trace_release		= acp_sof_trace_release,



	/* PM */

	.suspend                = amd_sof_acp_suspend,

	.resume                 = amd_sof_acp_resume,

};

EXPORT_SYMBOL_NS(sof_acp_common_ops, SND_SOC_SOF_AMD_COMMON);



MODULE_IMPORT_NS(SND_SOC_SOF_AMD_COMMON);

MODULE_DESCRIPTION("ACP SOF COMMON Driver");

MODULE_LICENSE("Dual BSD/GPL");

sound/soc/sof/amd/acp-dsp-offset.h

+20 −13
Original line number Diff line number Diff line
@@ -48,22 +48,29 @@ 
#define ACP_SOFT_RESET				0x1000

#define ACP_CONTROL				0x1004



#define ACP_I2S_PIN_CONFIG			0x1400

#define ACP3X_I2S_PIN_CONFIG			0x1400

#define ACP6X_I2S_PIN_CONFIG			0x1440



/* Registers from ACP_PGFSM block */

#define ACP_PGFSM_CONTROL			0x141C

#define ACP_PGFSM_STATUS			0x1420

#define ACP_CLKMUX_SEL				0x1424

/* Registers offsets from ACP_PGFSM block */

#define ACP3X_PGFSM_BASE			0x141C

#define ACP6X_PGFSM_BASE                        0x1024

#define PGFSM_CONTROL_OFFSET			0x0

#define PGFSM_STATUS_OFFSET			0x4

#define ACP3X_CLKMUX_SEL			0x1424

#define ACP6X_CLKMUX_SEL			0x102C



/* Registers from ACP_INTR block */

#define ACP_EXTERNAL_INTR_ENB			0x1800

#define ACP_EXTERNAL_INTR_CNTL			0x1804

#define ACP_EXTERNAL_INTR_STAT			0x1808

#define ACP_DSP_SW_INTR_CNTL			0x1814

#define ACP_DSP_SW_INTR_STAT                    0x1818

#define ACP_SW_INTR_TRIG                        0x181C

#define ACP3X_EXT_INTR_STAT			0x1808

#define ACP6X_EXT_INTR_STAT                     0x1A0C



#define ACP3X_DSP_SW_INTR_BASE			0x1814

#define ACP6X_DSP_SW_INTR_BASE                  0x1808

#define DSP_SW_INTR_CNTL_OFFSET			0x0

#define DSP_SW_INTR_STAT_OFFSET			0x4

#define DSP_SW_INTR_TRIG_OFFSET			0x8

#define ACP_ERROR_STATUS			0x18C4

#define ACP_AXI2DAGB_SEM_0			0x1880

#define ACP3X_AXI2DAGB_SEM_0			0x1880

#define ACP6X_AXI2DAGB_SEM_0			0x1874



/* Registers from ACP_SHA block */

#define ACP_SHA_DSP_FW_QUALIFIER		0x1C70
@@ -77,5 +84,5 @@ 
#define ACP_SHA_PSP_ACK                         0x1C74



#define ACP_SCRATCH_REG_0			0x10000



#define ACP6X_DSP_FUSION_RUNSTALL		0x0644

#endif