Commit 1db0016e authored by Weili Qian's avatar Weili Qian Committed by Herbert Xu
Browse files

crypto: hisilicon/qm - do not reset hardware when CE happens 



There is no need to reset hardware when Corrected Error(CE) happens.

Signed-off-by: default avatarWeili Qian <qianweili@huawei.com>
Reviewed-by: default avatarZaibo Xu <xuzaibo@huawei.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 87c35654

drivers/crypto/hisilicon/hpre/hpre_main.c

+1 −0
Original line number Diff line number Diff line
@@ -881,6 +881,7 @@ static const struct hisi_qm_err_ini hpre_err_ini = { 
		.fe			= 0,

		.ecc_2bits_mask		= HPRE_CORE_ECC_2BIT_ERR |

					  HPRE_OOO_ECC_2BIT_ERR,

		.dev_ce_mask		= HPRE_HAC_RAS_CE_ENABLE,

		.msi_wr_port		= HPRE_WR_MSI_PORT,

		.acpi_rst		= "HRST",

	}

drivers/crypto/hisilicon/qm.c

+17 −6
Original line number Diff line number Diff line
@@ -1612,7 +1612,7 @@ static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status) 


static enum acc_err_result qm_hw_error_handle_v2(struct hisi_qm *qm)

{

	u32 error_status, tmp;

	u32 error_status, tmp, val;



	/* read err sts */

	tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
@@ -1623,9 +1623,13 @@ static enum acc_err_result qm_hw_error_handle_v2(struct hisi_qm *qm) 
			qm->err_status.is_qm_ecc_mbit = true;



		qm_log_hw_error(qm, error_status);

		if (error_status == QM_DB_RANDOM_INVALID) {

		val = error_status | QM_DB_RANDOM_INVALID | QM_BASE_CE;

		/* ce error does not need to be reset */

		if (val == (QM_DB_RANDOM_INVALID | QM_BASE_CE)) {

			writel(error_status, qm->io_base +

			       QM_ABNORMAL_INT_SOURCE);

			writel(qm->err_ini->err_info.nfe,

			       qm->io_base + QM_RAS_NFE_ENABLE);

			return ACC_ERR_RECOVERED;

		}
@@ -3317,12 +3321,19 @@ static enum acc_err_result qm_dev_err_handle(struct hisi_qm *qm) 
		if (err_sts & qm->err_ini->err_info.ecc_2bits_mask)

			qm->err_status.is_dev_ecc_mbit = true;



		if (!qm->err_ini->log_dev_hw_err) {

			dev_err(&qm->pdev->dev, "Device doesn't support log hw error!\n");

			return ACC_ERR_NEED_RESET;

		if (qm->err_ini->log_dev_hw_err)

			qm->err_ini->log_dev_hw_err(qm, err_sts);



		/* ce error does not need to be reset */

		if ((err_sts | qm->err_ini->err_info.dev_ce_mask) ==

		     qm->err_ini->err_info.dev_ce_mask) {

			if (qm->err_ini->clear_dev_hw_err_status)

				qm->err_ini->clear_dev_hw_err_status(qm,

								err_sts);



			return ACC_ERR_RECOVERED;

		}



		qm->err_ini->log_dev_hw_err(qm, err_sts);

		return ACC_ERR_NEED_RESET;

	}

drivers/crypto/hisilicon/qm.h

+1 −0
Original line number Diff line number Diff line
@@ -173,6 +173,7 @@ struct hisi_qm_err_info { 
	char *acpi_rst;

	u32 msi_wr_port;

	u32 ecc_2bits_mask;

	u32 dev_ce_mask;

	u32 ce;

	u32 nfe;

	u32 fe;

drivers/crypto/hisilicon/sec2/sec_main.c

+1 −0
Original line number Diff line number Diff line
@@ -752,6 +752,7 @@ static const struct hisi_qm_err_ini sec_err_ini = { 
				  QM_ACC_WB_NOT_READY_TIMEOUT,

		.fe		= 0,

		.ecc_2bits_mask	= SEC_CORE_INT_STATUS_M_ECC,

		.dev_ce_mask	= SEC_RAS_CE_ENB_MSK,

		.msi_wr_port	= BIT(0),

		.acpi_rst	= "SRST",

	}

drivers/crypto/hisilicon/zip/zip_main.c

+4 −1
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ 
#define HZIP_CORE_INT_STATUS_M_ECC	BIT(1)

#define HZIP_CORE_SRAM_ECC_ERR_INFO	0x301148

#define HZIP_CORE_INT_RAS_CE_ENB	0x301160

#define HZIP_CORE_INT_RAS_CE_ENABLE	0x1

#define HZIP_CORE_INT_RAS_NFE_ENB	0x301164

#define HZIP_CORE_INT_RAS_FE_ENB        0x301168

#define HZIP_CORE_INT_RAS_NFE_ENABLE	0x7FE
@@ -327,7 +328,8 @@ static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 
	writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE);



	/* configure error type */

	writel(0x1, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);

	writel(HZIP_CORE_INT_RAS_CE_ENABLE,

	       qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);

	writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);

	writel(HZIP_CORE_INT_RAS_NFE_ENABLE,

	       qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
@@ -727,6 +729,7 @@ static const struct hisi_qm_err_ini hisi_zip_err_ini = { 
					  QM_ACC_WB_NOT_READY_TIMEOUT,

		.fe			= 0,

		.ecc_2bits_mask		= HZIP_CORE_INT_STATUS_M_ECC,

		.dev_ce_mask		= HZIP_CORE_INT_RAS_CE_ENABLE,

		.msi_wr_port		= HZIP_WR_PORT,

		.acpi_rst		= "ZRST",

	}