Commit 1da9d6e3 authored by Pavel Pisa's avatar Pavel Pisa Committed by Marc Kleine-Budde
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dt-bindings: net: can: binding for CTU CAN FD open-source IP core.

The device-tree bindings for open-source/open-hardware CAN FD IP core
designed at the Czech Technical University in Prague.

CTU CAN FD IP core and other CTU CAN bus related projects
listing and documentation page

   http://canbus.pages.fel.cvut.cz/

Link: https://lore.kernel.org/all/c5a37fc470ae065b21e79caa65863539393c0d7c.1647904780.git.pisa@cmp.felk.cvut.cz


Signed-off-by: default avatarPavel Pisa <pisa@cmp.felk.cvut.cz>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarPavel Machek <pavel@ucw.cz>
Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent fb23e43a
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: CTU CAN FD Open-source IP Core Device Tree Bindings

description: |
  Open-source CAN FD IP core developed at the Czech Technical University in Prague

  The core sources and documentation on project page
    [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
    [2] datasheet : https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf

  Integration in Xilinx Zynq SoC based system together with
  OpenCores SJA1000 compatible controllers
    [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
  Martin Jerabek dimploma thesis with integration and testing
  framework description
    [4] PDF : https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-canfd.pdf

maintainers:
  - Pavel Pisa <pisa@cmp.felk.cvut.cz>
  - Ondrej Ille <ondrej.ille@gmail.com>
  - Martin Jerabek <martin.jerabek01@gmail.com>

properties:
  compatible:
    oneOf:
      - items:
          - const: ctu,ctucanfd-2
          - const: ctu,ctucanfd
      - const: ctu,ctucanfd

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    description: |
      phandle of reference clock (100 MHz is appropriate
      for FPGA implementation on Zynq-7000 system).
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    ctu_can_fd_0: can@43c30000 {
      compatible = "ctu,ctucanfd";
      interrupts = <0 30 4>;
      clocks = <&clkc 15>;
      reg = <0x43c30000 0x10000>;
    };