Commit 1d86abf1 authored by Pali Rohár's avatar Pali Rohár Committed by Lorenzo Pieralisi
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PCI: aardvark: Replace custom PCIE_CORE_INT_* macros with PCI_INTERRUPT_* 

Header file linux/pci.h defines enum pci_interrupt_pin with corresponding
PCI_INTERRUPT_* values.

Link: https://lore.kernel.org/r/20220110015018.26359-2-kabel@kernel.org


Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Signed-off-by: default avatarMarek Behún <kabel@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent e783362e

drivers/pci/controller/pci-aardvark.c

+1 −5
Original line number Diff line number Diff line
@@ -38,10 +38,6 @@ 
#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN			BIT(6)

#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHCK			BIT(7)

#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV			BIT(8)

#define     PCIE_CORE_INT_A_ASSERT_ENABLE			1

#define     PCIE_CORE_INT_B_ASSERT_ENABLE			2

#define     PCIE_CORE_INT_C_ASSERT_ENABLE			3

#define     PCIE_CORE_INT_D_ASSERT_ENABLE			4

/* PIO registers base address and register offsets */

#define PIO_BASE_ADDR				0x4000

#define PIO_CTRL				(PIO_BASE_ADDR + 0x0)
@@ -959,7 +955,7 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) 
	bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);



	/* Support interrupt A for MSI feature */

	bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;

	bridge->conf.intpin = PCI_INTERRUPT_INTA;



	/* Aardvark HW provides PCIe Capability structure in version 2 */

	bridge->pcie_conf.cap = cpu_to_le16(2);