Commit 1d84b487 authored by Andrew Halaney's avatar Andrew Halaney Committed by Paolo Abeni
Browse files

net: stmmac: Pass stmmac_priv in some callbacks 



Passing stmmac_priv to some of the callbacks allows hwif implementations
to grab some data that platforms can customize. Adjust the callbacks
accordingly in preparation of such a platform customization.

Signed-off-by: default avatarAndrew Halaney <ahalaney@redhat.com>
Reviewed-by: default avatarJesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: default avatarBrian Masney <bmasney@redhat.com>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 0c3f3c4f

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

+24 −12
Original line number Diff line number Diff line
@@ -304,7 +304,8 @@ static void sun8i_dwmac_dma_init(void __iomem *ioaddr, 
	writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);

}



static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr,

static void sun8i_dwmac_dma_init_rx(struct stmmac_priv *priv,

				    void __iomem *ioaddr,

				    struct stmmac_dma_cfg *dma_cfg,

				    dma_addr_t dma_rx_phy, u32 chan)

{
@@ -312,7 +313,8 @@ static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr, 
	writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST);

}



static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr,

static void sun8i_dwmac_dma_init_tx(struct stmmac_priv *priv,

				    void __iomem *ioaddr,

				    struct stmmac_dma_cfg *dma_cfg,

				    dma_addr_t dma_tx_phy, u32 chan)

{
@@ -324,7 +326,8 @@ static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr, 
 * Called from stmmac_dma_ops->dump_regs

 * Used for ethtool

 */

static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space)

static void sun8i_dwmac_dump_regs(struct stmmac_priv *priv,

				  void __iomem *ioaddr, u32 *reg_space)

{

	int i;
@@ -352,7 +355,8 @@ static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, 
	}

}



static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan,

static void sun8i_dwmac_enable_dma_irq(struct stmmac_priv *priv,

				       void __iomem *ioaddr, u32 chan,

				       bool rx, bool tx)

{

	u32 value = readl(ioaddr + EMAC_INT_EN);
@@ -365,7 +369,8 @@ static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, 
	writel(value, ioaddr + EMAC_INT_EN);

}



static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan,

static void sun8i_dwmac_disable_dma_irq(struct stmmac_priv *priv,

					void __iomem *ioaddr, u32 chan,

					bool rx, bool tx)

{

	u32 value = readl(ioaddr + EMAC_INT_EN);
@@ -378,7 +383,8 @@ static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, 
	writel(value, ioaddr + EMAC_INT_EN);

}



static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)

static void sun8i_dwmac_dma_start_tx(struct stmmac_priv *priv,

				     void __iomem *ioaddr, u32 chan)

{

	u32 v;
@@ -398,7 +404,8 @@ static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) 
	writel(v, ioaddr + EMAC_TX_CTL1);

}



static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)

static void sun8i_dwmac_dma_stop_tx(struct stmmac_priv *priv,

				    void __iomem *ioaddr, u32 chan)

{

	u32 v;
@@ -407,7 +414,8 @@ static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) 
	writel(v, ioaddr + EMAC_TX_CTL1);

}



static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)

static void sun8i_dwmac_dma_start_rx(struct stmmac_priv *priv,

				     void __iomem *ioaddr, u32 chan)

{

	u32 v;
@@ -417,7 +425,8 @@ static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) 
	writel(v, ioaddr + EMAC_RX_CTL1);

}



static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)

static void sun8i_dwmac_dma_stop_rx(struct stmmac_priv *priv,

				    void __iomem *ioaddr, u32 chan)

{

	u32 v;
@@ -426,7 +435,8 @@ static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) 
	writel(v, ioaddr + EMAC_RX_CTL1);

}



static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,

static int sun8i_dwmac_dma_interrupt(struct stmmac_priv *priv,

				     void __iomem *ioaddr,

				     struct stmmac_extra_stats *x, u32 chan,

				     u32 dir)

{
@@ -492,7 +502,8 @@ static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, 
	return ret;

}



static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode,

static void sun8i_dwmac_dma_operation_mode_rx(struct stmmac_priv *priv,

					      void __iomem *ioaddr, int mode,

					      u32 channel, int fifosz, u8 qmode)

{

	u32 v;
@@ -515,7 +526,8 @@ static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode, 
	writel(v, ioaddr + EMAC_RX_CTL1);

}



static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode,

static void sun8i_dwmac_dma_operation_mode_tx(struct stmmac_priv *priv,

					      void __iomem *ioaddr, int mode,

					      u32 channel, int fifosz, u8 qmode)

{

	u32 v;

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

+2 −1
Original line number Diff line number Diff line
@@ -414,7 +414,8 @@ static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv) 
	dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);

}



static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,

static void dwmac1000_debug(struct stmmac_priv *priv, void __iomem *ioaddr,

			    struct stmmac_extra_stats *x,

			    u32 rx_queues, u32 tx_queues)

{

	u32 value = readl(ioaddr + GMAC_DEBUG);

drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c

+12 −7
Original line number Diff line number Diff line
@@ -110,7 +110,8 @@ static void dwmac1000_dma_init(void __iomem *ioaddr, 
	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);

}



static void dwmac1000_dma_init_rx(void __iomem *ioaddr,

static void dwmac1000_dma_init_rx(struct stmmac_priv *priv,

				  void __iomem *ioaddr,

				  struct stmmac_dma_cfg *dma_cfg,

				  dma_addr_t dma_rx_phy, u32 chan)

{
@@ -118,7 +119,8 @@ static void dwmac1000_dma_init_rx(void __iomem *ioaddr, 
	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);

}



static void dwmac1000_dma_init_tx(void __iomem *ioaddr,

static void dwmac1000_dma_init_tx(struct stmmac_priv *priv,

				  void __iomem *ioaddr,

				  struct stmmac_dma_cfg *dma_cfg,

				  dma_addr_t dma_tx_phy, u32 chan)

{
@@ -147,7 +149,8 @@ static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz) 
	return csr6;

}



static void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode,

static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv,

					    void __iomem *ioaddr, int mode,

					    u32 channel, int fifosz, u8 qmode)

{

	u32 csr6 = readl(ioaddr + DMA_CONTROL);
@@ -175,7 +178,8 @@ static void dwmac1000_dma_operation_mode_rx(void __iomem *ioaddr, int mode, 
	writel(csr6, ioaddr + DMA_CONTROL);

}



static void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode,

static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv,

					    void __iomem *ioaddr, int mode,

					    u32 channel, int fifosz, u8 qmode)

{

	u32 csr6 = readl(ioaddr + DMA_CONTROL);
@@ -208,7 +212,8 @@ static void dwmac1000_dma_operation_mode_tx(void __iomem *ioaddr, int mode, 
	writel(csr6, ioaddr + DMA_CONTROL);

}



static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)

static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv,

				    void __iomem *ioaddr, u32 *reg_space)

{

	int i;
@@ -263,8 +268,8 @@ static int dwmac1000_get_hw_feature(void __iomem *ioaddr, 
	return 0;

}



static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt,

				  u32 queue)

static void dwmac1000_rx_watchdog(struct stmmac_priv *priv,

				  void __iomem *ioaddr, u32 riwt, u32 queue)

{

	writel(riwt, ioaddr + DMA_RX_WATCHDOG);

}

drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c

+6 −4
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ static void dwmac100_dma_init(void __iomem *ioaddr, 
	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);

}



static void dwmac100_dma_init_rx(void __iomem *ioaddr,

static void dwmac100_dma_init_rx(struct stmmac_priv *priv, void __iomem *ioaddr,

				 struct stmmac_dma_cfg *dma_cfg,

				 dma_addr_t dma_rx_phy, u32 chan)

{
@@ -37,7 +37,7 @@ static void dwmac100_dma_init_rx(void __iomem *ioaddr, 
	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);

}



static void dwmac100_dma_init_tx(void __iomem *ioaddr,

static void dwmac100_dma_init_tx(struct stmmac_priv *priv, void __iomem *ioaddr,

				 struct stmmac_dma_cfg *dma_cfg,

				 dma_addr_t dma_tx_phy, u32 chan)

{
@@ -50,7 +50,8 @@ static void dwmac100_dma_init_tx(void __iomem *ioaddr, 
 * The transmit threshold can be programmed by setting the TTC bits in the DMA

 * control register.

 */

static void dwmac100_dma_operation_mode_tx(void __iomem *ioaddr, int mode,

static void dwmac100_dma_operation_mode_tx(struct stmmac_priv *priv,

					   void __iomem *ioaddr, int mode,

					   u32 channel, int fifosz, u8 qmode)

{

	u32 csr6 = readl(ioaddr + DMA_CONTROL);
@@ -65,7 +66,8 @@ static void dwmac100_dma_operation_mode_tx(void __iomem *ioaddr, int mode, 
	writel(csr6, ioaddr + DMA_CONTROL);

}



static void dwmac100_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)

static void dwmac100_dump_dma_regs(struct stmmac_priv *priv,

				   void __iomem *ioaddr, u32 *reg_space)

{

	int i;

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

+9 −5
Original line number Diff line number Diff line
@@ -198,7 +198,8 @@ static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw, 
	writel(value, ioaddr + MTL_OPERATION_MODE);

}



static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,

static void dwmac4_set_mtl_tx_queue_weight(struct stmmac_priv *priv,

					   struct mac_device_info *hw,

					   u32 weight, u32 queue)

{

	void __iomem *ioaddr = hw->pcsr;
@@ -227,7 +228,8 @@ static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan) 
	}

}



static void dwmac4_config_cbs(struct mac_device_info *hw,

static void dwmac4_config_cbs(struct stmmac_priv *priv,

			      struct mac_device_info *hw,

			      u32 send_slope, u32 idle_slope,

			      u32 high_credit, u32 low_credit, u32 queue)

{
@@ -253,7 +255,7 @@ static void dwmac4_config_cbs(struct mac_device_info *hw, 
	writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));



	/* configure idle slope (same register as tx weight) */

	dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);

	dwmac4_set_mtl_tx_queue_weight(priv, hw, idle_slope, queue);



	/* configure high credit */

	value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
@@ -759,7 +761,8 @@ static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x) 
	}

}



static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)

static int dwmac4_irq_mtl_status(struct stmmac_priv *priv,

				 struct mac_device_info *hw, u32 chan)

{

	void __iomem *ioaddr = hw->pcsr;

	u32 mtl_int_qx_status;
@@ -833,7 +836,8 @@ static int dwmac4_irq_status(struct mac_device_info *hw, 
	return ret;

}



static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,

static void dwmac4_debug(struct stmmac_priv *priv, void __iomem *ioaddr,

			 struct stmmac_extra_stats *x,

			 u32 rx_queues, u32 tx_queues)

{

	u32 value;