Commit 1d789535 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: convert IP version array to include instances 



Allow us to query instances versions more cleanly.

Instancing support is not consistent unfortunately. SDMA is a
good example.  Sienna cichlid has 4 total SDMA instances, each
enumerated separately (HWIDs 42, 43, 68, 69).  Arcturus has 8
total SDMA instances, but they are enumerated as multiple
instances of the same HWIDs (4x HWID 42, 4x HWID 43).  UMC
is another example.  On most chips there are multiple
instances with the same HWID.  This allows us to support both
forms.

v2: rebase
v3: clarify instancing support

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d0761fd2

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −1
Original line number Diff line number Diff line
@@ -1096,7 +1096,7 @@ struct amdgpu_device { 
	struct pci_saved_state          *pci_state;



	struct amdgpu_reset_control     *reset_cntl;

	uint32_t                        ip_versions[HW_ID_MAX];

	uint32_t                        ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE];

};



static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+140 −131
Original line number Diff line number Diff line
@@ -384,7 +384,16 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 
							hw_id_names[le16_to_cpu(ip->hw_id)]);

					adev->reg_offset[hw_ip][ip->number_instance] =

						ip->base_address;

					adev->ip_versions[hw_ip] =

					/* Instance support is somewhat inconsistent.

					 * SDMA is a good example.  Sienna cichlid has 4 total

					 * SDMA instances, each enumerated separately (HWIDs

					 * 42, 43, 68, 69).  Arcturus has 8 total SDMA instances,

					 * but they are enumerated as multiple instances of the

					 * same HWIDs (4x HWID 42, 4x HWID 43).  UMC is another

					 * example.  On most chips there are multiple instances

					 * with the same HWID.

					 */

					adev->ip_versions[hw_ip][ip->number_instance] =

						IP_VERSION(ip->major, ip->minor, ip->revision);

				}

			}
@@ -539,139 +548,139 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case CHIP_VEGA10:

		vega10_reg_base_init(adev);

		adev->sdma.num_instances = 2;

		adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 0, 0);

		adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 0, 0);

		adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 0);

		adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 0);

		adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 0);

		adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);

		adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 1, 0);

		adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 0, 0);

		adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);

		adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);

		adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);

		adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 0);

		adev->ip_versions[GC_HWIP] = IP_VERSION(9, 0, 1);

		adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);

		adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);

		adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 0);

		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);

		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);

		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);

		adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);

		adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);

		adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);

		adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);

		adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);

		adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);

		adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);

		adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);

		adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);

		adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);

		adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);

		adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);

		adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);

		break;

	case CHIP_VEGA12:

		vega10_reg_base_init(adev);

		adev->sdma.num_instances = 2;

		adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 3, 0);

		adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 3, 0);

		adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 0, 1);

		adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 0, 1);

		adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 0, 1);

		adev->ip_versions[DF_HWIP] = IP_VERSION(2, 5, 0);

		adev->ip_versions[NBIO_HWIP] = IP_VERSION(6, 2, 0);

		adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 0);

		adev->ip_versions[MP0_HWIP] = IP_VERSION(9, 0, 0);

		adev->ip_versions[MP1_HWIP] = IP_VERSION(9, 0, 0);

		adev->ip_versions[THM_HWIP] = IP_VERSION(9, 0, 0);

		adev->ip_versions[SMUIO_HWIP] = IP_VERSION(9, 0, 1);

		adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 1);

		adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 0, 0);

		adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 0, 0);

		adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 0, 1);

		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);

		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);

		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);

		adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);

		adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);

		adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);

		adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);

		adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);

		adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);

		adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);

		adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);

		adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);

		adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);

		adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);

		adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);

		adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);

		break;

	case CHIP_RAVEN:

		vega10_reg_base_init(adev);

		adev->sdma.num_instances = 1;

		adev->vcn.num_vcn_inst = 1;

		if (adev->apu_flags & AMD_APU_IS_RAVEN2) {

			adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 2, 0);

			adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 2, 0);

			adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 1);

			adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 1);

			adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 1);

			adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 1);

			adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 1);

			adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 5, 0);

			adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 1);

			adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 1);

			adev->ip_versions[THM_HWIP] = IP_VERSION(10, 1, 0);

			adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 1);

			adev->ip_versions[GC_HWIP] = IP_VERSION(9, 2, 2);

			adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 1);

			adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 1);

			adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);

			adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);

			adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);

			adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);

			adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);

			adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);

			adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);

			adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);

			adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);

			adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);

			adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);

			adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);

			adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);

			adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);

			adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);

		} else {

			adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 1, 0);

			adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 1, 0);

			adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 1, 0);

			adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 1, 0);

			adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 1, 0);

			adev->ip_versions[DF_HWIP] = IP_VERSION(2, 1, 0);

			adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 0, 0);

			adev->ip_versions[UMC_HWIP] = IP_VERSION(7, 0, 0);

			adev->ip_versions[MP0_HWIP] = IP_VERSION(10, 0, 0);

			adev->ip_versions[MP1_HWIP] = IP_VERSION(10, 0, 0);

			adev->ip_versions[THM_HWIP] = IP_VERSION(10, 0, 0);

			adev->ip_versions[SMUIO_HWIP] = IP_VERSION(10, 0, 0);

			adev->ip_versions[GC_HWIP] = IP_VERSION(9, 1, 0);

			adev->ip_versions[UVD_HWIP] = IP_VERSION(1, 0, 0);

			adev->ip_versions[DCE_HWIP] = IP_VERSION(1, 0, 0);

			adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);

			adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);

			adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);

			adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);

			adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);

			adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);

			adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);

			adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);

			adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);

			adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);

			adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);

			adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);

			adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);

			adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);

			adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);

		}

		break;

	case CHIP_VEGA20:

		vega20_reg_base_init(adev);

		adev->sdma.num_instances = 2;

		adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 0);

		adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 0);

		adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 0);

		adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 0);

		adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 0);

		adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 0);

		adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 0);

		adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 1);

		adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 2);

		adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);

		adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 2);

		adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 2);

		adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 0);

		adev->ip_versions[UVD_HWIP] = IP_VERSION(7, 2, 0);

		adev->ip_versions[VCE_HWIP] = IP_VERSION(4, 1, 0);

		adev->ip_versions[DCI_HWIP] = IP_VERSION(12, 1, 0);

		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);

		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);

		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);

		adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);

		adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);

		adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);

		adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);

		adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);

		adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);

		adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);

		adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);

		adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);

		adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);

		adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);

		adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);

		adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);

		break;

	case CHIP_ARCTURUS:

		arct_reg_base_init(adev);

		adev->sdma.num_instances = 8;

		adev->vcn.num_vcn_inst = 2;

		adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 1);

		adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 1);

		adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 2, 1);

		adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 2, 1);

		adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 2, 2);

		adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 1);

		adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 1);

		adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 1, 2);

		adev->ip_versions[MP0_HWIP] = IP_VERSION(11, 0, 4);

		adev->ip_versions[MP1_HWIP] = IP_VERSION(11, 0, 2);

		adev->ip_versions[THM_HWIP] = IP_VERSION(11, 0, 3);

		adev->ip_versions[SMUIO_HWIP] = IP_VERSION(11, 0, 3);

		adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 1);

		adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 5, 0);

		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);

		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);

		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);

		adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);

		adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);

		adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);

		adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);

		adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);

		adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);

		adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);

		adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);

		adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);

		adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);

		adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);

		break;

	case CHIP_ALDEBARAN:

		aldebaran_reg_base_init(adev);

		adev->sdma.num_instances = 5;

		adev->vcn.num_vcn_inst = 2;

		adev->ip_versions[MMHUB_HWIP] = IP_VERSION(9, 4, 2);

		adev->ip_versions[ATHUB_HWIP] = IP_VERSION(9, 4, 2);

		adev->ip_versions[OSSSYS_HWIP] = IP_VERSION(4, 4, 0);

		adev->ip_versions[HDP_HWIP] = IP_VERSION(4, 4, 0);

		adev->ip_versions[SDMA0_HWIP] = IP_VERSION(4, 4, 0);

		adev->ip_versions[DF_HWIP] = IP_VERSION(3, 6, 2);

		adev->ip_versions[NBIO_HWIP] = IP_VERSION(7, 4, 4);

		adev->ip_versions[UMC_HWIP] = IP_VERSION(6, 7, 0);

		adev->ip_versions[MP0_HWIP] = IP_VERSION(13, 0, 2);

		adev->ip_versions[MP1_HWIP] = IP_VERSION(13, 0, 2);

		adev->ip_versions[THM_HWIP] = IP_VERSION(13, 0, 2);

		adev->ip_versions[SMUIO_HWIP] = IP_VERSION(13, 0, 2);

		adev->ip_versions[GC_HWIP] = IP_VERSION(9, 4, 2);

		adev->ip_versions[UVD_HWIP] = IP_VERSION(2, 6, 0);

		adev->ip_versions[XGMI_HWIP] = IP_VERSION(6, 1, 0);

		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);

		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);

		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);

		adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);

		adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);

		adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);

		adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);

		adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);

		adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);

		adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);

		adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);

		adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);

		adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);

		adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);

		adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);

		break;

	default:

		r = amdgpu_discovery_reg_base_init(adev);
@@ -687,7 +696,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		break;

	}



	switch (adev->ip_versions[GC_HWIP]) {

	switch (adev->ip_versions[GC_HWIP][0]) {

	case IP_VERSION(9, 0, 1):

	case IP_VERSION(9, 2, 1):

	case IP_VERSION(9, 4, 0):
@@ -720,11 +729,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		return -EINVAL;

	}



	if (adev->ip_versions[XGMI_HWIP] == IP_VERSION(4, 8, 0))

	if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))

		adev->gmc.xgmi.supported = true;



	/* set NBIO version */

	switch (adev->ip_versions[NBIO_HWIP]) {

	switch (adev->ip_versions[NBIO_HWIP][0]) {

	case IP_VERSION(6, 1, 0):

	case IP_VERSION(6, 2, 0):

		adev->nbio.funcs = &nbio_v6_1_funcs;
@@ -763,7 +772,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		break;

	}



	switch (adev->ip_versions[HDP_HWIP]) {

	switch (adev->ip_versions[HDP_HWIP][0]) {

	case IP_VERSION(4, 0, 0):

	case IP_VERSION(4, 0, 1):

	case IP_VERSION(4, 1, 0):
@@ -785,7 +794,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		break;

	}



	switch (adev->ip_versions[DF_HWIP]) {

	switch (adev->ip_versions[DF_HWIP][0]) {

	case IP_VERSION(3, 6, 0):

	case IP_VERSION(3, 6, 1):

	case IP_VERSION(3, 6, 2):
@@ -802,7 +811,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		break;

	}



	switch (adev->ip_versions[SMUIO_HWIP]) {

	switch (adev->ip_versions[SMUIO_HWIP][0]) {

	case IP_VERSION(9, 0, 0):

	case IP_VERSION(9, 0, 1):

	case IP_VERSION(10, 0, 0):
@@ -833,7 +842,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	}



	/* what IP to use for this? */

	switch (adev->ip_versions[GC_HWIP]) {

	switch (adev->ip_versions[GC_HWIP][0]) {

	case IP_VERSION(9, 0, 1):

	case IP_VERSION(9, 1, 0):

	case IP_VERSION(9, 2, 1):
@@ -861,7 +870,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	}



	/* use GC or MMHUB IP version */

	switch (adev->ip_versions[GC_HWIP]) {

	switch (adev->ip_versions[GC_HWIP][0]) {

	case IP_VERSION(9, 0, 1):

	case IP_VERSION(9, 1, 0):

	case IP_VERSION(9, 2, 1):
@@ -888,7 +897,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		return -EINVAL;

	}



	switch (adev->ip_versions[OSSSYS_HWIP]) {

	switch (adev->ip_versions[OSSSYS_HWIP][0]) {

	case IP_VERSION(4, 0, 0):

	case IP_VERSION(4, 0, 1):

	case IP_VERSION(4, 1, 0):
@@ -914,7 +923,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	}



	if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {

		switch (adev->ip_versions[MP0_HWIP]) {

		switch (adev->ip_versions[MP0_HWIP][0]) {

		case IP_VERSION(9, 0, 0):

			amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);

			break;
@@ -952,7 +961,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	}



	if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {

		switch (adev->ip_versions[MP1_HWIP]) {

		switch (adev->ip_versions[MP1_HWIP][0]) {

		case IP_VERSION(9, 0, 0):

		case IP_VERSION(10, 0, 0):

		case IP_VERSION(10, 0, 1):
@@ -989,8 +998,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {

		amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

	} else if (adev->ip_versions[DCE_HWIP]) {

		switch (adev->ip_versions[DCE_HWIP]) {

	} else if (adev->ip_versions[DCE_HWIP][0]) {

		switch (adev->ip_versions[DCE_HWIP][0]) {

		case IP_VERSION(1, 0, 0):

		case IP_VERSION(1, 0, 1):

		case IP_VERSION(2, 0, 2):
@@ -1009,8 +1018,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		default:

			return -EINVAL;

		}

	} else if (adev->ip_versions[DCI_HWIP]) {

		switch (adev->ip_versions[DCI_HWIP]) {

	} else if (adev->ip_versions[DCI_HWIP][0]) {

		switch (adev->ip_versions[DCI_HWIP][0]) {

		case IP_VERSION(12, 0, 0):

		case IP_VERSION(12, 0, 1):

		case IP_VERSION(12, 1, 0):
@@ -1021,7 +1030,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		}

	}

#endif

	switch (adev->ip_versions[GC_HWIP]) {

	switch (adev->ip_versions[GC_HWIP][0]) {

	case IP_VERSION(9, 0, 1):

	case IP_VERSION(9, 1, 0):

	case IP_VERSION(9, 2, 1):
@@ -1048,7 +1057,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		return -EINVAL;

	}



	switch (adev->ip_versions[SDMA0_HWIP]) {

	switch (adev->ip_versions[SDMA0_HWIP][0]) {

	case IP_VERSION(4, 0, 0):

	case IP_VERSION(4, 0, 1):

	case IP_VERSION(4, 1, 0):
@@ -1078,7 +1087,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	}



	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {

		switch (adev->ip_versions[MP1_HWIP]) {

		switch (adev->ip_versions[MP1_HWIP][0]) {

		case IP_VERSION(9, 0, 0):

		case IP_VERSION(10, 0, 0):

		case IP_VERSION(10, 0, 1):
@@ -1112,8 +1121,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		}

	}



	if (adev->ip_versions[VCE_HWIP]) {

		switch (adev->ip_versions[UVD_HWIP]) {

	if (adev->ip_versions[VCE_HWIP][0]) {

		switch (adev->ip_versions[UVD_HWIP][0]) {

		case IP_VERSION(7, 0, 0):

		case IP_VERSION(7, 2, 0):

			amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
@@ -1121,7 +1130,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
		default:

			return -EINVAL;

		}

		switch (adev->ip_versions[VCE_HWIP]) {

		switch (adev->ip_versions[VCE_HWIP][0]) {

		case IP_VERSION(4, 0, 0):

		case IP_VERSION(4, 1, 0):

			amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
@@ -1130,7 +1139,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
			return -EINVAL;

		}

	} else {

		switch (adev->ip_versions[UVD_HWIP]) {

		switch (adev->ip_versions[UVD_HWIP][0]) {

		case IP_VERSION(1, 0, 0):

		case IP_VERSION(1, 0, 1):

			amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
@@ -1167,7 +1176,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	}



	if (adev->enable_mes) {

		switch (adev->ip_versions[GC_HWIP]) {

		switch (adev->ip_versions[GC_HWIP][0]) {

		case IP_VERSION(10, 1, 10):

		case IP_VERSION(10, 1, 1):

		case IP_VERSION(10, 1, 2):

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+17 −17
Original line number Diff line number Diff line
@@ -76,7 +76,7 @@ static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp 
		return;

	}



	switch (adev->ip_versions[MP0_HWIP]) {

	switch (adev->ip_versions[MP0_HWIP][0]) {

	case IP_VERSION(11, 0, 4):

	case IP_VERSION(11, 0, 7):

	case IP_VERSION(11, 0, 9):
@@ -97,7 +97,7 @@ static int psp_early_init(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct psp_context *psp = &adev->psp;



	switch (adev->ip_versions[MP0_HWIP]) {

	switch (adev->ip_versions[MP0_HWIP][0]) {

	case IP_VERSION(9, 0, 0):

		psp_v3_1_set_psp_funcs(psp);

		psp->autoload_supported = false;
@@ -279,7 +279,7 @@ static int psp_sw_init(void *handle) 
			return ret;

		}

	} else if (amdgpu_sriov_vf(adev) &&

		   adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2)) {

		   adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2)) {

		ret = psp_init_ta_microcode(psp, "aldebaran");

		if (ret) {

			DRM_ERROR("Failed to initialize ta microcode!\n");
@@ -322,8 +322,8 @@ static int psp_sw_init(void *handle) 
		}

	}



	if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||

	    adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7)) {

	if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||

	    adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {

		ret= psp_sysfs_init(adev);

		if (ret) {

			return ret;
@@ -353,8 +353,8 @@ static int psp_sw_fini(void *handle) 
		psp->ta_fw = NULL;

	}



	if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 0) ||

	    adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7))

	if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||

	    adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))

		psp_sysfs_fini(adev);



	kfree(cmd);
@@ -613,7 +613,7 @@ static int psp_tmr_init(struct psp_context *psp) 


static bool psp_skip_tmr(struct psp_context *psp)

{

	switch (psp->adev->ip_versions[MP0_HWIP]) {

	switch (psp->adev->ip_versions[MP0_HWIP][0]) {

	case IP_VERSION(11, 0, 9):

	case IP_VERSION(11, 0, 7):

	case IP_VERSION(13, 0, 2):
@@ -1010,8 +1010,8 @@ int psp_xgmi_terminate(struct psp_context *psp) 
	struct amdgpu_device *adev = psp->adev;



	/* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */

	if (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||

	    (adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&

	if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||

	    (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&

	     adev->gmc.xgmi.connected_to_cpu))

		return 0;
@@ -1113,7 +1113,7 @@ int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 


static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)

{

	return psp->adev->ip_versions[MP0_HWIP] == IP_VERSION(13, 0, 2) &&

	return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&

		psp->xgmi_context.context.bin_desc.feature_version >= 0x2000000b;

}
@@ -2232,8 +2232,8 @@ static int psp_load_smu_fw(struct psp_context *psp) 


	if ((amdgpu_in_reset(adev) &&

	     ras && adev->ras_enabled &&

	     (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 4) ||

	      adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 2)))) {

	     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||

	      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {

		ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);

		if (ret) {

			DRM_WARN("Failed to set MP1 state prepare for reload\n");
@@ -2330,9 +2330,9 @@ static int psp_load_non_psp_fw(struct psp_context *psp) 
			continue;



		if (psp->autoload_supported &&

		    (adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 7) ||

		     adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 11) ||

		     adev->ip_versions[MP0_HWIP] == IP_VERSION(11, 0, 12)) &&

		    (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||

		     adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||

		     adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&

		    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||

		     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||

		     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
@@ -2920,7 +2920,7 @@ static int psp_init_sos_base_fw(struct amdgpu_device *adev) 
		le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);



	if (adev->gmc.xgmi.connected_to_cpu ||

	    (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2))) {

	    (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {

		adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);

		adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

+2 −2
Original line number Diff line number Diff line
@@ -86,7 +86,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 
	for (i = 0; i < adev->vcn.num_vcn_inst; i++)

		atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);



	switch (adev->ip_versions[UVD_HWIP]) {

	switch (adev->ip_versions[UVD_HWIP][0]) {

	case IP_VERSION(1, 0, 0):

	case IP_VERSION(1, 0, 1):

		if (adev->apu_flags & AMD_APU_IS_RAVEN2)
@@ -134,7 +134,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 
			adev->vcn.indirect_sram = true;

		break;

	case IP_VERSION(3, 0, 0):

		if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0))

		if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))

			fw_name = FIRMWARE_SIENNA_CICHLID;

		else

			fw_name = FIRMWARE_NAVY_FLOUNDER;

drivers/gpu/drm/amd/amdgpu/athub_v2_0.c

+1 −1
Original line number Diff line number Diff line
@@ -77,7 +77,7 @@ int athub_v2_0_set_clockgating(struct amdgpu_device *adev, 
	if (amdgpu_sriov_vf(adev))

		return 0;



	switch (adev->ip_versions[ATHUB_HWIP]) {

	switch (adev->ip_versions[ATHUB_HWIP][0]) {

	case IP_VERSION(2, 0, 0):

	case IP_VERSION(2, 0, 2):

		athub_v2_0_update_medium_grain_clock_gating(adev,