Commit 1d3e3c4e authored by Joseph Lo's avatar Joseph Lo Committed by Thierry Reding
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clk: tegra: Remove the old emc_mux clock for Tegra210 



Remove the old emc_mux clock and don't use the common EMC clock
definition. This will be replaced by a new clock defined in the
EMC driver.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 0ac65fc9

drivers/clk/tegra/clk-tegra210.c

+31 −19
Original line number Diff line number Diff line
@@ -319,12 +319,6 @@ static unsigned long tegra210_input_freq[] = { 
	[8] = 12000000,

};



static const char *mux_pllmcp_clkm[] = {

	"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",

	"pll_p",

};

#define mux_pllmcp_clkm_idx NULL



#define PLL_ENABLE			(1 << 30)



#define PLLCX_MISC1_IDDQ		(1 << 27)
@@ -2336,7 +2330,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true },

	[tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true },

	[tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true },

	[tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true },

	[tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true },

	[tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true },

	[tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true },
@@ -2979,6 +2972,27 @@ static const char * const sor1_parents[] = { 


static u32 sor1_parents_idx[] = { 0, 2, 5, 6 };



static const struct clk_div_table mc_div_table_tegra210[] = {

	{ .val = 0, .div = 2 },

	{ .val = 1, .div = 4 },

	{ .val = 2, .div = 1 },

	{ .val = 3, .div = 2 },

	{ .val = 0, .div = 0 },

};



static void tegra210_clk_register_mc(const char *name,

				     const char *parent_name)

{

	struct clk *clk;



	clk = clk_register_divider_table(NULL, name, parent_name,

					 CLK_IS_CRITICAL,

					 clk_base + CLK_SOURCE_EMC,

					 15, 2, CLK_DIVIDER_READ_ONLY,

					 mc_div_table_tegra210, &emc_lock);

	clks[TEGRA210_CLK_MC] = clk;

}



static const char * const sor1_out_parents[] = {

	/*

	 * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so
@@ -3021,7 +3035,8 @@ static const char * const la_parents[] = { 
static struct tegra_clk_periph tegra210_la =

	TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, NULL);



static __init void tegra210_periph_clk_init(void __iomem *clk_base,

static __init void tegra210_periph_clk_init(struct device_node *np,

					    void __iomem *clk_base,

					    void __iomem *pmc_base)

{

	struct clk *clk;
@@ -3067,16 +3082,6 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 
			CLK_SOURCE_LA, 0);

	clks[TEGRA210_CLK_LA] = clk;



	/* emc mux */

	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,

			       ARRAY_SIZE(mux_pllmcp_clkm), 0,

			       clk_base + CLK_SOURCE_EMC,

			       29, 3, 0, &emc_lock);



	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,

				    &emc_lock);

	clks[TEGRA210_CLK_MC] = clk;



	/* cml0 */

	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,

				0, 0, &pll_e_lock);
@@ -3119,6 +3124,13 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 
	}



	tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);



	/* emc */

	clk = tegra210_clk_register_emc(np, clk_base);

	clks[TEGRA210_CLK_EMC] = clk;



	/* mc */

	tegra210_clk_register_mc("mc", "emc");

}



static void __init tegra210_pll_init(void __iomem *clk_base,
@@ -3717,7 +3729,7 @@ static void __init tegra210_clock_init(struct device_node *np) 


	tegra_fixed_clk_init(tegra210_clks);

	tegra210_pll_init(clk_base, pmc_base);

	tegra210_periph_clk_init(clk_base, pmc_base);

	tegra210_periph_clk_init(np, clk_base, pmc_base);

	tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,

			     tegra210_audio_plls,

			     ARRAY_SIZE(tegra210_audio_plls), 24576000);