Commit 1d32f5d6 authored by Anusha Srivatsa's avatar Anusha Srivatsa
Browse files

drm/i915/display: Introduce HAS_CDCLK_SQUASH macro 



Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.

Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221025223042.138810-2-anusha.srivatsa@intel.com
parent c74b644f

drivers/gpu/drm/i915/display/intel_cdclk.c

+5 −10
Original line number Diff line number Diff line
@@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 
	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);

}



static bool has_cdclk_squash(struct drm_i915_private *i915)

{

	return IS_DG2(i915);

}



struct intel_cdclk_vals {

	u32 cdclk;

	u16 refclk;
@@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 
		return;

	}



	if (has_cdclk_squash(dev_priv))

	if (HAS_CDCLK_SQUASH(dev_priv))

		squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);



	if (squash_ctl & CDCLK_SQUASH_ENABLE) {
@@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
	else

		clock = cdclk;



	if (has_cdclk_squash(dev_priv)) {

	if (HAS_CDCLK_SQUASH(dev_priv)) {

		u32 squash_ctl = 0;



		if (waveform)
@@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 
	expected = skl_cdclk_decimal(cdclk);



	/* Figure out what CD2X divider we should be using for this cdclk */

	if (has_cdclk_squash(dev_priv))

	if (HAS_CDCLK_SQUASH(dev_priv))

		clock = dev_priv->display.cdclk.hw.vco / 2;

	else

		clock = dev_priv->display.cdclk.hw.cdclk;
@@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, 
	 * the moment all platforms with squasher use a fixed cd2x

	 * divider.

	 */

	if (!has_cdclk_squash(dev_priv))

	if (!HAS_CDCLK_SQUASH(dev_priv))

		return false;



	return a->cdclk != b->cdclk &&
@@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, 
	 * the moment all platforms with squasher use a fixed cd2x

	 * divider.

	 */

	if (has_cdclk_squash(dev_priv))

	if (HAS_CDCLK_SQUASH(dev_priv))

		return false;



	return a->cdclk != b->cdclk &&

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -865,6 +865,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 
#define HAS_DOUBLE_BUFFERED_M_N(dev_priv)	(DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))



#define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)

#define HAS_CDCLK_SQUASH(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_squash)

#define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)

#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)

#define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)

drivers/gpu/drm/i915/i915_pci.c

+1 −0
Original line number Diff line number Diff line
@@ -1063,6 +1063,7 @@ static const struct intel_device_info xehpsdv_info = { 
	.has_heci_pxp = 1, \

	.needs_compact_pt = 1, \

	.has_media_ratio_mode = 1, \

	.display.has_cdclk_squash = 1, \

	.__runtime.platform_engine_mask = \

		BIT(RCS0) | BIT(BCS0) | \

		BIT(VECS0) | BIT(VECS1) | \

drivers/gpu/drm/i915/intel_device_info.h

+1 −0
Original line number Diff line number Diff line
@@ -179,6 +179,7 @@ enum intel_ppgtt_type { 
	/* Keep in alphabetical order */ \

	func(cursor_needs_physical); \

	func(has_cdclk_crawl); \

	func(has_cdclk_squash); \

	func(has_ddi); \

	func(has_dp_mst); \

	func(has_dsb); \