Commit 1d2577ab authored Aug 22, 2022 by Marcus Carlberg Committed by Jakub Kicinski Aug 26, 2022

net: dsa: mv88e6xxx: support RGMII cmode



Since the probe defaults all interfaces to the highest speed possible
(10GBASE-X in mv88e6393x) before the phy mode configuration from the
devicetree is considered it is currently impossible to use port 0 in
RGMII mode.

This change will allow RGMII modes to be configurable for port 0
enabling port 0 to be configured as RGMII as well as serial depending
on configuration.

Signed-off-by: Marcus Carlberg <marcus.carlberg@axis.com>
Link: https://lore.kernel.org/r/20220822144136.16627-1-marcus.carlberg@axis.com


Signed-off-by: Jakub Kicinski <kuba@kernel.org>

parent 44387d17

drivers/net/dsa/mv88e6xxx/chip.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -816,6 +816,14 @@ static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
		MAC_10000FD;
		}
		}

		if (port == 0) {
		__set_bit(PHY_INTERFACE_MODE_RMII, supported);
		__set_bit(PHY_INTERFACE_MODE_RGMII, supported);
		__set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
		__set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
		__set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
		}
		}

		static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,

drivers/net/dsa/mv88e6xxx/port.c

+19 −0

Original line number	Diff line number	Diff line
		@@ -517,6 +517,12 @@ static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
		case PHY_INTERFACE_MODE_RMII:
		cmode = MV88E6XXX_PORT_STS_CMODE_RMII;
		break;
		case PHY_INTERFACE_MODE_RGMII:
		case PHY_INTERFACE_MODE_RGMII_ID:
		case PHY_INTERFACE_MODE_RGMII_RXID:
		case PHY_INTERFACE_MODE_RGMII_TXID:
		cmode = MV88E6XXX_PORT_STS_CMODE_RGMII;
		break;
		case PHY_INTERFACE_MODE_1000BASEX:
		cmode = MV88E6XXX_PORT_STS_CMODE_1000BASEX;
		break;
		@@ -634,6 +640,19 @@ int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
		if (port != 0 && port != 9 && port != 10)
		return -EOPNOTSUPP;

		if (port == 9 \|\| port == 10) {
		switch (mode) {
		case PHY_INTERFACE_MODE_RMII:
		case PHY_INTERFACE_MODE_RGMII:
		case PHY_INTERFACE_MODE_RGMII_ID:
		case PHY_INTERFACE_MODE_RGMII_RXID:
		case PHY_INTERFACE_MODE_RGMII_TXID:
		return -EINVAL;
		default:
		break;
		}
		}

		/* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */
		err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, &reg);
		if (err)