Commit 1d02ae4e authored by Asad Kamal's avatar Asad Kamal Committed by Alex Deucher
Browse files

drm/amd/pm: Update pci link width for smu v13.0.6 



Update addresses of PCIE link width registers,
& link width format used to populate gpu metrics
table for smu v13.0.6

v2:
Removed ESM register update

v3:
Updated patch subject and message

Signed-off-by: default avatarAsad Kamal <asad.kamal@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dd12b858

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

+8 −2
Original line number Diff line number Diff line
@@ -81,9 +81,10 @@ 
#define EPSILON 1



#define smnPCIE_ESM_CTRL 0x193D0

#define smnPCIE_LC_LINK_WIDTH_CNTL 0x1ab40288

#define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4

#define MAX_LINK_WIDTH 6



static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {

	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage,			0),
@@ -1947,6 +1948,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table 
	struct amdgpu_device *adev = smu->adev;

	int ret = 0, inst0, xcc0;

	MetricsTable_t *metrics;

	u16 link_width_level;



	inst0 = adev->sdma.instance[0].aid_id;

	xcc0 = GET_INST(GC, 0);
@@ -1997,8 +1999,12 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table 
	gpu_metrics->throttle_status = 0;



	if (!(adev->flags & AMD_IS_APU)) {

		link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);

		if (link_width_level > MAX_LINK_WIDTH)

			link_width_level = 0;



		gpu_metrics->pcie_link_width =

			smu_v13_0_6_get_current_pcie_link_width_level(smu);

			DECODE_LANE_WIDTH(link_width_level);

		gpu_metrics->pcie_link_speed =

			smu_v13_0_6_get_current_pcie_link_speed(smu);

	}