Commit 1cc1e851 authored by Suniel Mahesh's avatar Suniel Mahesh Committed by Heiko Stuebner
Browse files

arm64: dts: rockchip: Add BT support on px30-engicam 



Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have
an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected
on the UART bus.

UART bus on the design routed via USB to UART CP20x bridge. This
bridge powered from 3V3 regualtor gpio.

This patch adds BT enablement nodes for these respective boards.

Signed-off-by: default avatarMichael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: default avatarSuniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: default avatarJagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20201109181017.206834-7-jagan@amarulasolutions.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 93a4e7d1

arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -24,6 +24,18 @@ 
		pinctrl-0 = <&wifi_enable_h>;

	};



	vcc3v3_btreg: vcc3v3-btreg {

		compatible = "regulator-gpio";

		enable-active-high;

		pinctrl-names = "default";

		pinctrl-0 = <&bt_enable_h>;

		regulator-name = "btreg-gpio-supply";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		regulator-always-on;

		states = <3300000 0x0>;

	};



	vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {

		compatible = "regulator-fixed";

		regulator-name = "vcc3v3_rf_aux_mod";

arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -8,6 +8,12 @@ 
#include "px30-engicam-common.dtsi"



&pinctrl {

	bt {

		bt_enable_h: bt-enable-h {

			rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;

		};

	};



	sdio-pwrseq {

		wifi_enable_h: wifi-enable-h {

			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -18,3 +24,7 @@ 
&sdio_pwrseq {

	reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;

};



&vcc3v3_btreg {

	enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;

};

arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts

+10 −0
Original line number Diff line number Diff line
@@ -21,6 +21,12 @@ 
};



&pinctrl {

	bt {

		bt_enable_h: bt-enable-h {

			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;

		};

	};



	sdio-pwrseq {

		wifi_enable_h: wifi-enable-h {

			rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -31,3 +37,7 @@ 
&sdio_pwrseq {

	reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;

};



&vcc3v3_btreg {

	enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;

};