Commit 1c4d9d5b authored by Wojciech Ziemba's avatar Wojciech Ziemba Committed by Herbert Xu
Browse files

crypto: qat - enable detection of accelerators hang 



Enable the detection of hangs by setting watchdog timers (WDTs) on
generations that supports that feature.

The default timeout value comes from HW specs. WTDs are reset each time
an accelerator wins arbitration and is able to send/read a command to/from
an accelerator.

The value has added significant margin to make sure there are no spurious
timeouts. The scope of watchdog is per QAT device.

If a timeout is detected, the firmware resets the accelerator and
returns a response descriptor with an appropriate error code.

Signed-off-by: default avatarWojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 7e958d30

drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c

+1 −0
Original line number Diff line number Diff line
@@ -224,6 +224,7 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data) 
	hw_data->uof_get_name = uof_get_name;

	hw_data->uof_get_ae_mask = uof_get_ae_mask;

	hw_data->set_msix_rttable = set_msix_default_rttable;

	hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;



	adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);

}

drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c

+1 −0
Original line number Diff line number Diff line
@@ -212,6 +212,7 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data) 
	hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms;

	hw_data->reset_device = adf_reset_flr;

	hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;

	hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;

	adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

}

drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c

+1 −0
Original line number Diff line number Diff line
@@ -214,6 +214,7 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data) 
	hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms;

	hw_data->reset_device = adf_reset_flr;

	hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;

	hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;

	adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

}

drivers/crypto/qat/qat_common/adf_accel_devices.h

+1 −0
Original line number Diff line number Diff line
@@ -173,6 +173,7 @@ struct adf_hw_device_data { 
	void (*configure_iov_threads)(struct adf_accel_dev *accel_dev,

				      bool enable);

	void (*enable_ints)(struct adf_accel_dev *accel_dev);

	void (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);

	int (*enable_vf2pf_comms)(struct adf_accel_dev *accel_dev);

	void (*reset_device)(struct adf_accel_dev *accel_dev);

	void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);

drivers/crypto/qat/qat_common/adf_gen2_hw_data.c

+25 −0
Original line number Diff line number Diff line
@@ -179,3 +179,28 @@ u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev) 
	return capabilities;

}

EXPORT_SYMBOL_GPL(adf_gen2_get_accel_cap);



void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)

{

	struct adf_hw_device_data *hw_data = accel_dev->hw_device;

	u32 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE;

	u32 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;

	unsigned long accel_mask = hw_data->accel_mask;

	void __iomem *pmisc_addr;

	struct adf_bar *pmisc;

	int pmisc_id;

	u32 i = 0;



	pmisc_id = hw_data->get_misc_bar_id(hw_data);

	pmisc = &GET_BARS(accel_dev)[pmisc_id];

	pmisc_addr = pmisc->virt_addr;



	/* Configures WDT timers */

	for_each_set_bit(i, &accel_mask, hw_data->num_accel) {

		/* Enable WDT for sym and dc */

		ADF_CSR_WR(pmisc_addr, ADF_SSMWDT(i), timer_val);

		/* Enable WDT for pke */

		ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKE(i), timer_val_pke);

	}

}

EXPORT_SYMBOL_GPL(adf_gen2_set_ssm_wdtimer);