Commit 1c4b5ecb authored by Christoph Hellwig's avatar Christoph Hellwig
Browse files

remove the h8300 architecture 



Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
parent 5c1ee569

Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt

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* Renesas H8/300 divider clock



Required Properties:



  - compatible: Must be "renesas,h8300-div-clock"



  - clocks: Reference to the parent clocks ("extal1" and "extal2")



  - #clock-cells: Must be 1



  - reg: Base address and length of the divide rate selector



  - renesas,width: bit width of selector



Example

-------



		cclk: cclk {

			compatible = "renesas,h8300-div-clock";

			clocks = <&xclk>;

			#clock-cells = <0>;

			reg = <0xfee01b 2>;

			renesas,width = <2>;

		};

Documentation/devicetree/bindings/h8300/cpu.txt

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* H8/300 CPU bindings



Required properties:



- compatible: Compatible property value should be "renesas,h8300".

- clock-frequency: Contains the clock frequency for CPU, in Hz.



Example:



		cpu@0 {

			compatible = "renesas,h8300";

			clock-frequency = <20000000>;

		};

Documentation/devicetree/bindings/interrupt-controller/renesas,h8300h-intc.txt

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* H8/300H Interrupt controller



Required properties:



- compatible: has to be "renesas,h8300h-intc", "renesas,h8300-intc" as fallback.

- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in

  interrupts.txt in this directory

- regs: Base address of interrupt controller registers.



Optional properties:



- any properties, listed in interrupts.txt, and any standard resource allocation

  properties



Example:



	h8intc: interrupt-controller@fee012 {

		compatible = "renesas,h8300h-intc", "renesas,h8300-intc";

		#interrupt-cells = <2>;

		interrupt-controller;

		reg = <0xfee012 7>;

	};

Documentation/devicetree/bindings/interrupt-controller/renesas,h8s-intc.txt

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* H8S Interrupt controller



Required properties:



- compatible: has to be "renesas,h8s-intc", "renesas,h8300-intc" as fallback.

- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in

  interrupts.txt in this directory

- regs: Base address of interrupt controller registers.



Optional properties:



- any properties, listed in interrupts.txt, and any standard resource allocation

  properties



Example:



	h8intc: interrupt-controller@fffe00 {

		compatible = "renesas,h8s-intc", "renesas,h8300-intc";

		#interrupt-cells = <2>;

		interrupt-controller;

		reg = <0xfffe00 24>;

	};

Documentation/devicetree/bindings/memory-controllers/renesas,h8300-bsc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/renesas,h8300-bsc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: H8/300 bus controller



maintainers:

  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

  - Yoshinori Sato <ysato@users.sourceforge.jp>



properties:

  compatible:

    items:

      - enum:

          - renesas,h8300h-bsc

          - renesas,h8s-bsc

      - const: renesas,h8300-bsc



  reg:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    memory-controller@fee01e {

        compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";

        reg = <0xfee01e 8>;

    };