Unverified Commit 1c351c23 authored by Mark Brown's avatar Mark Brown
Browse files

spi: switch to use modern name (part4) 

Merge series from Yang Yingliang <yangyingliang@huawei.com>:

I'm trying to rename the legacy name to modern name used in SPI drivers,
this is part4 patchset.

After introducing devm_spi_alloc_host/spi_alloc_host(), the legacy
named function devm_spi_alloc_master/spi_alloc_master() can be replaced.
And also change other legacy name master/slave to modern name host/target
or controller. Each patch compile test passed.
parents 246f74bb 557efcf4

drivers/spi/spi-orion.c

+45 −45
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ struct orion_child_options { 
};



struct orion_spi {

	struct spi_master	*master;

	struct spi_controller	*host;

	void __iomem		*base;

	struct clk              *clk;

	struct clk              *axi_clk;
@@ -141,7 +141,7 @@ static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) 
	struct orion_spi *orion_spi;

	const struct orion_spi_dev *devdata;



	orion_spi = spi_master_get_devdata(spi->master);

	orion_spi = spi_controller_get_devdata(spi->controller);

	devdata = orion_spi->devdata;



	tclk_hz = clk_get_rate(orion_spi->clk);
@@ -235,7 +235,7 @@ orion_spi_mode_set(struct spi_device *spi) 
	u32 reg;

	struct orion_spi *orion_spi;



	orion_spi = spi_master_get_devdata(spi->master);

	orion_spi = spi_controller_get_devdata(spi->controller);



	reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));

	reg &= ~ORION_SPI_MODE_MASK;
@@ -257,7 +257,7 @@ orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed) 
	u32 reg;

	struct orion_spi *orion_spi;



	orion_spi = spi_master_get_devdata(spi->master);

	orion_spi = spi_controller_get_devdata(spi->controller);



	/*

	 * Erratum description: (Erratum NO. FE-9144572) The device
@@ -297,7 +297,7 @@ orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 
	unsigned int bits_per_word = spi->bits_per_word;

	int	rc;



	orion_spi = spi_master_get_devdata(spi->master);

	orion_spi = spi_controller_get_devdata(spi->controller);



	if ((t != NULL) && t->speed_hz)

		speed = t->speed_hz;
@@ -330,7 +330,7 @@ static void orion_spi_set_cs(struct spi_device *spi, bool enable) 
	void __iomem *ctrl_reg;

	u32 val;



	orion_spi = spi_master_get_devdata(spi->master);

	orion_spi = spi_controller_get_devdata(spi->controller);

	ctrl_reg = spi_reg(orion_spi, ORION_SPI_IF_CTRL_REG);



	val = readl(ctrl_reg);
@@ -388,7 +388,7 @@ orion_spi_write_read_8bit(struct spi_device *spi, 


	cs_single_byte = spi->mode & SPI_CS_WORD;



	orion_spi = spi_master_get_devdata(spi->master);

	orion_spi = spi_controller_get_devdata(spi->controller);



	if (cs_single_byte)

		orion_spi_set_cs(spi, 0);
@@ -439,7 +439,7 @@ orion_spi_write_read_16bit(struct spi_device *spi, 
		return -1;

	}



	orion_spi = spi_master_get_devdata(spi->master);

	orion_spi = spi_controller_get_devdata(spi->controller);

	tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);

	rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);

	int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
@@ -475,7 +475,7 @@ orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) 
	word_len = spi->bits_per_word;

	count = xfer->len;



	orion_spi = spi_master_get_devdata(spi->master);

	orion_spi = spi_controller_get_devdata(spi->controller);



	/*

	 * Use SPI direct write mode if base address is available
@@ -528,7 +528,7 @@ orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) 
	return xfer->len - count;

}



static int orion_spi_transfer_one(struct spi_master *master,

static int orion_spi_transfer_one(struct spi_controller *host,

					struct spi_device *spi,

					struct spi_transfer *t)

{
@@ -548,7 +548,7 @@ static int orion_spi_setup(struct spi_device *spi) 
{

	int ret;

#ifdef CONFIG_PM

	struct orion_spi *orion_spi = spi_master_get_devdata(spi->master);

	struct orion_spi *orion_spi = spi_controller_get_devdata(spi->controller);

	struct device *dev = orion_spi->dev;



	orion_spi_runtime_resume(dev);
@@ -644,44 +644,44 @@ MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); 
static int orion_spi_probe(struct platform_device *pdev)

{

	const struct orion_spi_dev *devdata;

	struct spi_master *master;

	struct spi_controller *host;

	struct orion_spi *spi;

	struct resource *r;

	unsigned long tclk_hz;

	int status = 0;

	struct device_node *np;



	master = spi_alloc_master(&pdev->dev, sizeof(*spi));

	if (master == NULL) {

		dev_dbg(&pdev->dev, "master allocation failed\n");

	host = spi_alloc_host(&pdev->dev, sizeof(*spi));

	if (host == NULL) {

		dev_dbg(&pdev->dev, "host allocation failed\n");

		return -ENOMEM;

	}



	if (pdev->id != -1)

		master->bus_num = pdev->id;

		host->bus_num = pdev->id;

	if (pdev->dev.of_node) {

		u32 cell_index;



		if (!of_property_read_u32(pdev->dev.of_node, "cell-index",

					  &cell_index))

			master->bus_num = cell_index;

			host->bus_num = cell_index;

	}



	/* we support all 4 SPI modes and LSB first option */

	master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_CS_WORD;

	master->set_cs = orion_spi_set_cs;

	master->transfer_one = orion_spi_transfer_one;

	master->num_chipselect = ORION_NUM_CHIPSELECTS;

	master->setup = orion_spi_setup;

	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);

	master->auto_runtime_pm = true;

	master->use_gpio_descriptors = true;

	master->flags = SPI_CONTROLLER_GPIO_SS;



	platform_set_drvdata(pdev, master);



	spi = spi_master_get_devdata(master);

	spi->master = master;

	host->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_CS_WORD;

	host->set_cs = orion_spi_set_cs;

	host->transfer_one = orion_spi_transfer_one;

	host->num_chipselect = ORION_NUM_CHIPSELECTS;

	host->setup = orion_spi_setup;

	host->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);

	host->auto_runtime_pm = true;

	host->use_gpio_descriptors = true;

	host->flags = SPI_CONTROLLER_GPIO_SS;



	platform_set_drvdata(pdev, host);



	spi = spi_controller_get_devdata(host);

	spi->host = host;

	spi->dev = &pdev->dev;



	devdata = device_get_match_data(&pdev->dev);
@@ -718,14 +718,14 @@ static int orion_spi_probe(struct platform_device *pdev) 
	 */

	if (of_device_is_compatible(pdev->dev.of_node,

					"marvell,armada-370-spi"))

		master->max_speed_hz = min(devdata->max_hz,

		host->max_speed_hz = min(devdata->max_hz,

				DIV_ROUND_UP(tclk_hz, devdata->min_divisor));

	else if (devdata->min_divisor)

		master->max_speed_hz =

		host->max_speed_hz =

			DIV_ROUND_UP(tclk_hz, devdata->min_divisor);

	else

		master->max_speed_hz = devdata->max_hz;

	master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);

		host->max_speed_hz = devdata->max_hz;

	host->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);



	spi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);

	if (IS_ERR(spi->base)) {
@@ -784,8 +784,8 @@ static int orion_spi_probe(struct platform_device *pdev) 
	if (status < 0)

		goto out_rel_pm;



	master->dev.of_node = pdev->dev.of_node;

	status = spi_register_master(master);

	host->dev.of_node = pdev->dev.of_node;

	status = spi_register_controller(host);

	if (status < 0)

		goto out_rel_pm;
@@ -798,21 +798,21 @@ static int orion_spi_probe(struct platform_device *pdev) 
out_rel_clk:

	clk_disable_unprepare(spi->clk);

out:

	spi_master_put(master);

	spi_controller_put(host);

	return status;

}





static void orion_spi_remove(struct platform_device *pdev)

{

	struct spi_master *master = platform_get_drvdata(pdev);

	struct orion_spi *spi = spi_master_get_devdata(master);

	struct spi_controller *host = platform_get_drvdata(pdev);

	struct orion_spi *spi = spi_controller_get_devdata(host);



	pm_runtime_get_sync(&pdev->dev);

	clk_disable_unprepare(spi->axi_clk);

	clk_disable_unprepare(spi->clk);



	spi_unregister_master(master);

	spi_unregister_controller(host);

	pm_runtime_disable(&pdev->dev);

}
@@ -821,8 +821,8 @@ MODULE_ALIAS("platform:" DRIVER_NAME); 
#ifdef CONFIG_PM

static int orion_spi_runtime_suspend(struct device *dev)

{

	struct spi_master *master = dev_get_drvdata(dev);

	struct orion_spi *spi = spi_master_get_devdata(master);

	struct spi_controller *host = dev_get_drvdata(dev);

	struct orion_spi *spi = spi_controller_get_devdata(host);



	clk_disable_unprepare(spi->axi_clk);

	clk_disable_unprepare(spi->clk);
@@ -831,8 +831,8 @@ static int orion_spi_runtime_suspend(struct device *dev) 


static int orion_spi_runtime_resume(struct device *dev)

{

	struct spi_master *master = dev_get_drvdata(dev);

	struct orion_spi *spi = spi_master_get_devdata(master);

	struct spi_controller *host = dev_get_drvdata(dev);

	struct orion_spi *spi = spi_controller_get_devdata(host);



	if (!IS_ERR(spi->axi_clk))

		clk_prepare_enable(spi->axi_clk);

drivers/spi/spi-pci1xxxx.c

+7 −7
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ struct pci1xxxx_spi_internal { 
	bool spi_xfer_in_progress;

	int irq;

	struct completion spi_xfer_done;

	struct spi_master *spi_host;

	struct spi_controller *spi_host;

	struct pci1xxxx_spi *parent;

	struct {

		unsigned int dev_sel : 3;
@@ -250,7 +250,7 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id * 
	struct pci1xxxx_spi_internal *spi_sub_ptr;

	struct device *dev = &pdev->dev;

	struct pci1xxxx_spi *spi_bus;

	struct spi_master *spi_host;

	struct spi_controller *spi_host;

	u32 regval;

	int ret;
@@ -276,7 +276,7 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id * 
						      sizeof(struct pci1xxxx_spi_internal),

						      GFP_KERNEL);

		spi_sub_ptr = spi_bus->spi_int[iter];

		spi_sub_ptr->spi_host = devm_spi_alloc_master(dev, sizeof(struct spi_master));

		spi_sub_ptr->spi_host = devm_spi_alloc_host(dev, sizeof(struct spi_controller));

		if (!spi_sub_ptr->spi_host)

			return -ENOMEM;
@@ -366,8 +366,8 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id * 
		spi_host->max_speed_hz = PCI1XXXX_SPI_MAX_CLOCK_HZ;

		spi_host->min_speed_hz = PCI1XXXX_SPI_MIN_CLOCK_HZ;

		spi_host->flags = SPI_CONTROLLER_MUST_TX;

		spi_master_set_devdata(spi_host, spi_sub_ptr);

		ret = devm_spi_register_master(dev, spi_host);

		spi_controller_set_devdata(spi_host, spi_sub_ptr);

		ret = devm_spi_register_controller(dev, spi_host);

		if (ret)

			goto error;

	}
@@ -415,7 +415,7 @@ static int pci1xxxx_spi_resume(struct device *dev) 


	for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {

		spi_sub_ptr = spi_ptr->spi_int[iter];

		spi_master_resume(spi_sub_ptr->spi_host);

		spi_controller_resume(spi_sub_ptr->spi_host);

		writel(regval, spi_ptr->reg_base +

		       SPI_MST_EVENT_MASK_REG_OFFSET(iter));
@@ -441,7 +441,7 @@ static int pci1xxxx_spi_suspend(struct device *dev) 


		/* Store existing config before suspend */

		store_restore_config(spi_ptr, spi_sub_ptr, iter, 1);

		spi_master_suspend(spi_sub_ptr->spi_host);

		spi_controller_suspend(spi_sub_ptr->spi_host);

		writel(reg1, spi_ptr->reg_base +

		       SPI_MST_EVENT_MASK_REG_OFFSET(iter));

	}

drivers/spi/spi-pic32-sqi.c

+43 −43
Original line number Diff line number Diff line
@@ -139,7 +139,7 @@ struct pic32_sqi { 
	void __iomem		*regs;

	struct clk		*sys_clk;

	struct clk		*base_clk; /* drives spi clock */

	struct spi_master	*master;

	struct spi_controller	*host;

	int			irq;

	struct completion	xfer_done;

	struct ring_desc	*ring;
@@ -316,9 +316,9 @@ static int pic32_sqi_one_transfer(struct pic32_sqi *sqi, 
	return 0;

}



static int pic32_sqi_prepare_hardware(struct spi_master *master)

static int pic32_sqi_prepare_hardware(struct spi_controller *host)

{

	struct pic32_sqi *sqi = spi_master_get_devdata(master);

	struct pic32_sqi *sqi = spi_controller_get_devdata(host);



	/* enable spi interface */

	pic32_setbits(sqi->regs + PESQI_CONF_REG, PESQI_EN);
@@ -328,7 +328,7 @@ static int pic32_sqi_prepare_hardware(struct spi_master *master) 
	return 0;

}



static bool pic32_sqi_can_dma(struct spi_master *master,

static bool pic32_sqi_can_dma(struct spi_controller *host,

			      struct spi_device *spi,

			      struct spi_transfer *x)

{
@@ -336,7 +336,7 @@ static bool pic32_sqi_can_dma(struct spi_master *master, 
	return true;

}



static int pic32_sqi_one_message(struct spi_master *master,

static int pic32_sqi_one_message(struct spi_controller *host,

				 struct spi_message *msg)

{

	struct spi_device *spi = msg->spi;
@@ -347,7 +347,7 @@ static int pic32_sqi_one_message(struct spi_master *master, 
	unsigned long timeout;

	u32 val;



	sqi = spi_master_get_devdata(master);

	sqi = spi_controller_get_devdata(host);



	reinit_completion(&sqi->xfer_done);

	msg->actual_length = 0;
@@ -412,7 +412,7 @@ static int pic32_sqi_one_message(struct spi_master *master, 
	/* wait for xfer completion */

	timeout = wait_for_completion_timeout(&sqi->xfer_done, 5 * HZ);

	if (timeout == 0) {

		dev_err(&sqi->master->dev, "wait timedout/interrupted\n");

		dev_err(&sqi->host->dev, "wait timedout/interrupted\n");

		ret = -ETIMEDOUT;

		msg->status = ret;

	} else {
@@ -434,14 +434,14 @@ static int pic32_sqi_one_message(struct spi_master *master, 
		/* release ring descr */

		ring_desc_put(sqi, rdesc);

	}

	spi_finalize_current_message(spi->master);

	spi_finalize_current_message(spi->controller);



	return ret;

}



static int pic32_sqi_unprepare_hardware(struct spi_master *master)

static int pic32_sqi_unprepare_hardware(struct spi_controller *host)

{

	struct pic32_sqi *sqi = spi_master_get_devdata(master);

	struct pic32_sqi *sqi = spi_controller_get_devdata(host);



	/* disable clk */

	pic32_clrbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN);
@@ -458,18 +458,18 @@ static int ring_desc_ring_alloc(struct pic32_sqi *sqi) 
	int i;



	/* allocate coherent DMAable memory for hardware buffer descriptors. */

	sqi->bd = dma_alloc_coherent(&sqi->master->dev,

	sqi->bd = dma_alloc_coherent(&sqi->host->dev,

				     sizeof(*bd) * PESQI_BD_COUNT,

				     &sqi->bd_dma, GFP_KERNEL);

	if (!sqi->bd) {

		dev_err(&sqi->master->dev, "failed allocating dma buffer\n");

		dev_err(&sqi->host->dev, "failed allocating dma buffer\n");

		return -ENOMEM;

	}



	/* allocate software ring descriptors */

	sqi->ring = kcalloc(PESQI_BD_COUNT, sizeof(*rdesc), GFP_KERNEL);

	if (!sqi->ring) {

		dma_free_coherent(&sqi->master->dev,

		dma_free_coherent(&sqi->host->dev,

				  sizeof(*bd) * PESQI_BD_COUNT,

				  sqi->bd, sqi->bd_dma);

		return -ENOMEM;
@@ -498,7 +498,7 @@ static int ring_desc_ring_alloc(struct pic32_sqi *sqi) 


static void ring_desc_ring_free(struct pic32_sqi *sqi)

{

	dma_free_coherent(&sqi->master->dev,

	dma_free_coherent(&sqi->host->dev,

			  sizeof(struct buf_desc) * PESQI_BD_COUNT,

			  sqi->bd, sqi->bd_dma);

	kfree(sqi->ring);
@@ -568,28 +568,28 @@ static void pic32_sqi_hw_init(struct pic32_sqi *sqi) 


static int pic32_sqi_probe(struct platform_device *pdev)

{

	struct spi_master *master;

	struct spi_controller *host;

	struct pic32_sqi *sqi;

	int ret;



	master = spi_alloc_master(&pdev->dev, sizeof(*sqi));

	if (!master)

	host = spi_alloc_host(&pdev->dev, sizeof(*sqi));

	if (!host)

		return -ENOMEM;



	sqi = spi_master_get_devdata(master);

	sqi->master = master;

	sqi = spi_controller_get_devdata(host);

	sqi->host = host;



	sqi->regs = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(sqi->regs)) {

		ret = PTR_ERR(sqi->regs);

		goto err_free_master;

		goto err_free_host;

	}



	/* irq */

	sqi->irq = platform_get_irq(pdev, 0);

	if (sqi->irq < 0) {

		ret = sqi->irq;

		goto err_free_master;

		goto err_free_host;

	}



	/* clocks */
@@ -597,27 +597,27 @@ static int pic32_sqi_probe(struct platform_device *pdev) 
	if (IS_ERR(sqi->sys_clk)) {

		ret = PTR_ERR(sqi->sys_clk);

		dev_err(&pdev->dev, "no sys_clk ?\n");

		goto err_free_master;

		goto err_free_host;

	}



	sqi->base_clk = devm_clk_get(&pdev->dev, "spi_ck");

	if (IS_ERR(sqi->base_clk)) {

		ret = PTR_ERR(sqi->base_clk);

		dev_err(&pdev->dev, "no base clk ?\n");

		goto err_free_master;

		goto err_free_host;

	}



	ret = clk_prepare_enable(sqi->sys_clk);

	if (ret) {

		dev_err(&pdev->dev, "sys clk enable failed\n");

		goto err_free_master;

		goto err_free_host;

	}



	ret = clk_prepare_enable(sqi->base_clk);

	if (ret) {

		dev_err(&pdev->dev, "base clk enable failed\n");

		clk_disable_unprepare(sqi->sys_clk);

		goto err_free_master;

		goto err_free_host;

	}



	init_completion(&sqi->xfer_done);
@@ -640,24 +640,24 @@ static int pic32_sqi_probe(struct platform_device *pdev) 
		goto err_free_ring;

	}



	/* register master */

	master->num_chipselect	= 2;

	master->max_speed_hz	= clk_get_rate(sqi->base_clk);

	master->dma_alignment	= 32;

	master->max_dma_len	= PESQI_BD_BUF_LEN_MAX;

	master->dev.of_node	= pdev->dev.of_node;

	master->mode_bits	= SPI_MODE_3 | SPI_MODE_0 | SPI_TX_DUAL |

	/* register host */

	host->num_chipselect	= 2;

	host->max_speed_hz	= clk_get_rate(sqi->base_clk);

	host->dma_alignment	= 32;

	host->max_dma_len	= PESQI_BD_BUF_LEN_MAX;

	host->dev.of_node	= pdev->dev.of_node;

	host->mode_bits		= SPI_MODE_3 | SPI_MODE_0 | SPI_TX_DUAL |

				  SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD;

	master->flags		= SPI_CONTROLLER_HALF_DUPLEX;

	master->can_dma		= pic32_sqi_can_dma;

	master->bits_per_word_mask	= SPI_BPW_RANGE_MASK(8, 32);

	master->transfer_one_message	= pic32_sqi_one_message;

	master->prepare_transfer_hardware	= pic32_sqi_prepare_hardware;

	master->unprepare_transfer_hardware	= pic32_sqi_unprepare_hardware;



	ret = devm_spi_register_master(&pdev->dev, master);

	host->flags		= SPI_CONTROLLER_HALF_DUPLEX;

	host->can_dma		= pic32_sqi_can_dma;

	host->bits_per_word_mask	= SPI_BPW_RANGE_MASK(8, 32);

	host->transfer_one_message	= pic32_sqi_one_message;

	host->prepare_transfer_hardware	= pic32_sqi_prepare_hardware;

	host->unprepare_transfer_hardware	= pic32_sqi_unprepare_hardware;



	ret = devm_spi_register_controller(&pdev->dev, host);

	if (ret) {

		dev_err(&master->dev, "failed registering spi master\n");

		dev_err(&host->dev, "failed registering spi host\n");

		free_irq(sqi->irq, sqi);

		goto err_free_ring;

	}
@@ -673,8 +673,8 @@ static int pic32_sqi_probe(struct platform_device *pdev) 
	clk_disable_unprepare(sqi->base_clk);

	clk_disable_unprepare(sqi->sys_clk);



err_free_master:

	spi_master_put(master);

err_free_host:

	spi_controller_put(host);

	return ret;

}

drivers/spi/spi-pic32.c

+77 −77
Original line number Diff line number Diff line
@@ -100,7 +100,7 @@ struct pic32_spi { 
	int			tx_irq;

	u32			fifo_n_byte; /* FIFO depth in bytes */

	struct clk		*clk;

	struct spi_master	*master;

	struct spi_controller	*host;

	/* Current controller setting */

	u32			speed_hz; /* spi-clk rate */

	u32			mode;
@@ -224,9 +224,9 @@ static void pic32_err_stop(struct pic32_spi *pic32s, const char *msg) 
	disable_irq_nosync(pic32s->tx_irq);



	/* Show err message and abort xfer with err */

	dev_err(&pic32s->master->dev, "%s\n", msg);

	if (pic32s->master->cur_msg)

		pic32s->master->cur_msg->status = -EIO;

	dev_err(&pic32s->host->dev, "%s\n", msg);

	if (pic32s->host->cur_msg)

		pic32s->host->cur_msg->status = -EIO;

	complete(&pic32s->xfer_done);

}
@@ -250,7 +250,7 @@ static irqreturn_t pic32_spi_fault_irq(int irq, void *dev_id) 
		return IRQ_HANDLED;

	}



	if (!pic32s->master->cur_msg) {

	if (!pic32s->host->cur_msg) {

		pic32_err_stop(pic32s, "err_irq: no mesg");

		return IRQ_NONE;

	}
@@ -300,16 +300,16 @@ static void pic32_spi_dma_rx_notify(void *data) 
static int pic32_spi_dma_transfer(struct pic32_spi *pic32s,

				  struct spi_transfer *xfer)

{

	struct spi_master *master = pic32s->master;

	struct spi_controller *host = pic32s->host;

	struct dma_async_tx_descriptor *desc_rx;

	struct dma_async_tx_descriptor *desc_tx;

	dma_cookie_t cookie;

	int ret;



	if (!master->dma_rx || !master->dma_tx)

	if (!host->dma_rx || !host->dma_tx)

		return -ENODEV;



	desc_rx = dmaengine_prep_slave_sg(master->dma_rx,

	desc_rx = dmaengine_prep_slave_sg(host->dma_rx,

					  xfer->rx_sg.sgl,

					  xfer->rx_sg.nents,

					  DMA_DEV_TO_MEM,
@@ -319,7 +319,7 @@ static int pic32_spi_dma_transfer(struct pic32_spi *pic32s, 
		goto err_dma;

	}



	desc_tx = dmaengine_prep_slave_sg(master->dma_tx,

	desc_tx = dmaengine_prep_slave_sg(host->dma_tx,

					  xfer->tx_sg.sgl,

					  xfer->tx_sg.nents,

					  DMA_MEM_TO_DEV,
@@ -343,13 +343,13 @@ static int pic32_spi_dma_transfer(struct pic32_spi *pic32s, 
	if (ret)

		goto err_dma_tx;



	dma_async_issue_pending(master->dma_rx);

	dma_async_issue_pending(master->dma_tx);

	dma_async_issue_pending(host->dma_rx);

	dma_async_issue_pending(host->dma_tx);



	return 0;



err_dma_tx:

	dmaengine_terminate_all(master->dma_rx);

	dmaengine_terminate_all(host->dma_rx);

err_dma:

	return ret;

}
@@ -357,7 +357,7 @@ static int pic32_spi_dma_transfer(struct pic32_spi *pic32s, 
static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width)

{

	int buf_offset = offsetof(struct pic32_spi_regs, buf);

	struct spi_master *master = pic32s->master;

	struct spi_controller *host = pic32s->host;

	struct dma_slave_config cfg;

	int ret;
@@ -371,16 +371,16 @@ static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width) 
	cfg.dst_addr_width = dma_width;

	/* tx channel */

	cfg.direction = DMA_MEM_TO_DEV;

	ret = dmaengine_slave_config(master->dma_tx, &cfg);

	ret = dmaengine_slave_config(host->dma_tx, &cfg);

	if (ret) {

		dev_err(&master->dev, "tx channel setup failed\n");

		dev_err(&host->dev, "tx channel setup failed\n");

		return ret;

	}

	/* rx channel */

	cfg.direction = DMA_DEV_TO_MEM;

	ret = dmaengine_slave_config(master->dma_rx, &cfg);

	ret = dmaengine_slave_config(host->dma_rx, &cfg);

	if (ret)

		dev_err(&master->dev, "rx channel setup failed\n");

		dev_err(&host->dev, "rx channel setup failed\n");



	return ret;

}
@@ -430,19 +430,19 @@ static int pic32_spi_set_word_size(struct pic32_spi *pic32s, u8 bits_per_word) 
	return 0;

}



static int pic32_spi_prepare_hardware(struct spi_master *master)

static int pic32_spi_prepare_hardware(struct spi_controller *host)

{

	struct pic32_spi *pic32s = spi_master_get_devdata(master);

	struct pic32_spi *pic32s = spi_controller_get_devdata(host);



	pic32_spi_enable(pic32s);



	return 0;

}



static int pic32_spi_prepare_message(struct spi_master *master,

static int pic32_spi_prepare_message(struct spi_controller *host,

				     struct spi_message *msg)

{

	struct pic32_spi *pic32s = spi_master_get_devdata(master);

	struct pic32_spi *pic32s = spi_controller_get_devdata(host);

	struct spi_device *spi = msg->spi;

	u32 val;
@@ -481,18 +481,18 @@ static int pic32_spi_prepare_message(struct spi_master *master, 
	return 0;

}



static bool pic32_spi_can_dma(struct spi_master *master,

static bool pic32_spi_can_dma(struct spi_controller *host,

			      struct spi_device *spi,

			      struct spi_transfer *xfer)

{

	struct pic32_spi *pic32s = spi_master_get_devdata(master);

	struct pic32_spi *pic32s = spi_controller_get_devdata(host);



	/* skip using DMA on small size transfer to avoid overhead.*/

	return (xfer->len >= PIC32_DMA_LEN_MIN) &&

	       test_bit(PIC32F_DMA_PREP, &pic32s->flags);

}



static int pic32_spi_one_transfer(struct spi_master *master,

static int pic32_spi_one_transfer(struct spi_controller *host,

				  struct spi_device *spi,

				  struct spi_transfer *transfer)

{
@@ -501,7 +501,7 @@ static int pic32_spi_one_transfer(struct spi_master *master, 
	unsigned long timeout;

	int ret;



	pic32s = spi_master_get_devdata(master);

	pic32s = spi_controller_get_devdata(host);



	/* handle transfer specific word size change */

	if (transfer->bits_per_word &&
@@ -549,8 +549,8 @@ static int pic32_spi_one_transfer(struct spi_master *master, 
	if (timeout == 0) {

		dev_err(&spi->dev, "wait error/timedout\n");

		if (dma_issued) {

			dmaengine_terminate_all(master->dma_rx);

			dmaengine_terminate_all(master->dma_tx);

			dmaengine_terminate_all(host->dma_rx);

			dmaengine_terminate_all(host->dma_tx);

		}

		ret = -ETIMEDOUT;

	} else {
@@ -560,16 +560,16 @@ static int pic32_spi_one_transfer(struct spi_master *master, 
	return ret;

}



static int pic32_spi_unprepare_message(struct spi_master *master,

static int pic32_spi_unprepare_message(struct spi_controller *host,

				       struct spi_message *msg)

{

	/* nothing to do */

	return 0;

}



static int pic32_spi_unprepare_hardware(struct spi_master *master)

static int pic32_spi_unprepare_hardware(struct spi_controller *host)

{

	struct pic32_spi *pic32s = spi_master_get_devdata(master);

	struct pic32_spi *pic32s = spi_controller_get_devdata(host);



	pic32_spi_disable(pic32s);
@@ -605,28 +605,28 @@ static void pic32_spi_cleanup(struct spi_device *spi) 


static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev)

{

	struct spi_master *master = pic32s->master;

	struct spi_controller *host = pic32s->host;

	int ret = 0;



	master->dma_rx = dma_request_chan(dev, "spi-rx");

	if (IS_ERR(master->dma_rx)) {

		if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER)

	host->dma_rx = dma_request_chan(dev, "spi-rx");

	if (IS_ERR(host->dma_rx)) {

		if (PTR_ERR(host->dma_rx) == -EPROBE_DEFER)

			ret = -EPROBE_DEFER;

		else

			dev_warn(dev, "RX channel not found.\n");



		master->dma_rx = NULL;

		host->dma_rx = NULL;

		goto out_err;

	}



	master->dma_tx = dma_request_chan(dev, "spi-tx");

	if (IS_ERR(master->dma_tx)) {

		if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER)

	host->dma_tx = dma_request_chan(dev, "spi-tx");

	if (IS_ERR(host->dma_tx)) {

		if (PTR_ERR(host->dma_tx) == -EPROBE_DEFER)

			ret = -EPROBE_DEFER;

		else

			dev_warn(dev, "TX channel not found.\n");



		master->dma_tx = NULL;

		host->dma_tx = NULL;

		goto out_err;

	}
@@ -639,14 +639,14 @@ static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev) 
	return 0;



out_err:

	if (master->dma_rx) {

		dma_release_channel(master->dma_rx);

		master->dma_rx = NULL;

	if (host->dma_rx) {

		dma_release_channel(host->dma_rx);

		host->dma_rx = NULL;

	}



	if (master->dma_tx) {

		dma_release_channel(master->dma_tx);

		master->dma_tx = NULL;

	if (host->dma_tx) {

		dma_release_channel(host->dma_tx);

		host->dma_tx = NULL;

	}



	return ret;
@@ -658,11 +658,11 @@ static void pic32_spi_dma_unprep(struct pic32_spi *pic32s) 
		return;



	clear_bit(PIC32F_DMA_PREP, &pic32s->flags);

	if (pic32s->master->dma_rx)

		dma_release_channel(pic32s->master->dma_rx);

	if (pic32s->host->dma_rx)

		dma_release_channel(pic32s->host->dma_rx);



	if (pic32s->master->dma_tx)

		dma_release_channel(pic32s->master->dma_tx);

	if (pic32s->host->dma_tx)

		dma_release_channel(pic32s->host->dma_tx);

}



static void pic32_spi_hw_init(struct pic32_spi *pic32s)
@@ -680,7 +680,7 @@ static void pic32_spi_hw_init(struct pic32_spi *pic32s) 
	/* disable framing mode */

	ctrl &= ~CTRL_FRMEN;



	/* enable master mode while disabled */

	/* enable host mode while disabled */

	ctrl |= CTRL_MSTEN;



	/* set tx fifo threshold interrupt */
@@ -752,36 +752,36 @@ static int pic32_spi_hw_probe(struct platform_device *pdev, 


static int pic32_spi_probe(struct platform_device *pdev)

{

	struct spi_master *master;

	struct spi_controller *host;

	struct pic32_spi *pic32s;

	int ret;



	master = spi_alloc_master(&pdev->dev, sizeof(*pic32s));

	if (!master)

	host = spi_alloc_host(&pdev->dev, sizeof(*pic32s));

	if (!host)

		return -ENOMEM;



	pic32s = spi_master_get_devdata(master);

	pic32s->master = master;

	pic32s = spi_controller_get_devdata(host);

	pic32s->host = host;



	ret = pic32_spi_hw_probe(pdev, pic32s);

	if (ret)

		goto err_master;



	master->dev.of_node	= pdev->dev.of_node;

	master->mode_bits	= SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH;

	master->num_chipselect	= 1; /* single chip-select */

	master->max_speed_hz	= clk_get_rate(pic32s->clk);

	master->setup		= pic32_spi_setup;

	master->cleanup		= pic32_spi_cleanup;

	master->flags		= SPI_CONTROLLER_MUST_TX | SPI_CONTROLLER_MUST_RX;

	master->bits_per_word_mask	= SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |

		goto err_host;



	host->dev.of_node	= pdev->dev.of_node;

	host->mode_bits	= SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH;

	host->num_chipselect	= 1; /* single chip-select */

	host->max_speed_hz	= clk_get_rate(pic32s->clk);

	host->setup		= pic32_spi_setup;

	host->cleanup		= pic32_spi_cleanup;

	host->flags		= SPI_CONTROLLER_MUST_TX | SPI_CONTROLLER_MUST_RX;

	host->bits_per_word_mask	= SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |

					  SPI_BPW_MASK(32);

	master->transfer_one		= pic32_spi_one_transfer;

	master->prepare_message		= pic32_spi_prepare_message;

	master->unprepare_message	= pic32_spi_unprepare_message;

	master->prepare_transfer_hardware	= pic32_spi_prepare_hardware;

	master->unprepare_transfer_hardware	= pic32_spi_unprepare_hardware;

	master->use_gpio_descriptors = true;

	host->transfer_one		= pic32_spi_one_transfer;

	host->prepare_message		= pic32_spi_prepare_message;

	host->unprepare_message	= pic32_spi_unprepare_message;

	host->prepare_transfer_hardware	= pic32_spi_prepare_hardware;

	host->unprepare_transfer_hardware	= pic32_spi_unprepare_hardware;

	host->use_gpio_descriptors = true;



	/* optional DMA support */

	ret = pic32_spi_dma_prep(pic32s, &pdev->dev);
@@ -789,7 +789,7 @@ static int pic32_spi_probe(struct platform_device *pdev) 
		goto err_bailout;



	if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))

		master->can_dma	= pic32_spi_can_dma;

		host->can_dma	= pic32_spi_can_dma;



	init_completion(&pic32s->xfer_done);

	pic32s->mode = -1;
@@ -824,10 +824,10 @@ static int pic32_spi_probe(struct platform_device *pdev) 
		goto err_bailout;

	}



	/* register master */

	ret = devm_spi_register_master(&pdev->dev, master);

	/* register host */

	ret = devm_spi_register_controller(&pdev->dev, host);

	if (ret) {

		dev_err(&master->dev, "failed registering spi master\n");

		dev_err(&host->dev, "failed registering spi host\n");

		goto err_bailout;

	}
@@ -838,8 +838,8 @@ static int pic32_spi_probe(struct platform_device *pdev) 
err_bailout:

	pic32_spi_dma_unprep(pic32s);

	clk_disable_unprepare(pic32s->clk);

err_master:

	spi_master_put(master);

err_host:

	spi_controller_put(host);

	return ret;

}

drivers/spi/spi-pl022.c

+47 −47

File changed.

Preview size limit exceeded, changes collapsed.