Commit 1c304680 authored by Artem Bityutskiy's avatar Artem Bityutskiy Committed by Jia, Yingbao
Browse files

intel_idle: add Granite Rapids Xeon support 

mainline inclusion
from mainline-v6.12
commit 370406bf5738dade8ac95a2ee95c29299d4ac902
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/IB1HDA
CVE: NA
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=370406bf5738dade8ac95a2ee95c29299d4ac902



-------------------------------------------------

Intel-SIG: commit 370406bf5738 intel_idle: add Granite Rapids Xeon support.
Backport for GNR intel_idle support and fix on 6.6

Add Granite Rapids Xeon C-states, which are C1, C1E, C6, and C6P.

Comparing to previous Xeon Generations (e.g., Emerald Rapids), C6
requests end up only in core C6 state, and no package C-state promotion
takes place even if all cores in the package are in core C6.

C6P requests also end up in core C6, but if all cores have requested
C6P, the SoC will enter the package C6 state.

Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Link: https://patch.msgid.link/20240806160310.3719205-1-artem.bityutskiy@linux.intel.com


[ rjw: Changelog edits ]
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
[ Yingbao Jia: amend commit log ]
Signed-off-by: default avatarYingbao Jia <yingbao.jia@intel.com>
parent 118ae39e

drivers/idle/intel_idle.c

+46 −0
Original line number Diff line number Diff line
@@ -993,6 +993,45 @@ static struct cpuidle_state spr_cstates[] __initdata = { 
		.enter = NULL }

};



static struct cpuidle_state gnr_cstates[] __initdata = {

	{

		.name = "C1",

		.desc = "MWAIT 0x00",

		.flags = MWAIT2flg(0x00),

		.exit_latency = 1,

		.target_residency = 1,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.name = "C1E",

		.desc = "MWAIT 0x01",

		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,

		.exit_latency = 4,

		.target_residency = 4,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.name = "C6",

		.desc = "MWAIT 0x20",

		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED |

					   CPUIDLE_FLAG_INIT_XSTATE,

		.exit_latency = 170,

		.target_residency = 650,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.name = "C6P",

		.desc = "MWAIT 0x21",

		.flags = MWAIT2flg(0x21) | CPUIDLE_FLAG_TLB_FLUSHED |

					   CPUIDLE_FLAG_INIT_XSTATE,

		.exit_latency = 210,

		.target_residency = 1000,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.enter = NULL }

};



static struct cpuidle_state atom_cstates[] __initdata = {

	{

		.name = "C1E",
@@ -1391,6 +1430,12 @@ static const struct idle_cpu idle_cpu_spr __initconst = { 
	.use_acpi = true,

};



static const struct idle_cpu idle_cpu_gnr __initconst = {

	.state_table = gnr_cstates,

	.disable_promotion_to_c1e = true,

	.use_acpi = true,

};



static const struct idle_cpu idle_cpu_avn __initconst = {

	.state_table = avn_cstates,

	.disable_promotion_to_c1e = true,
@@ -1464,6 +1509,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,	&idle_cpu_gmt),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&idle_cpu_spr),

	X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,	&idle_cpu_spr),

	X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_X,	&idle_cpu_gnr),

	X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL,	&idle_cpu_knl),

	X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM,	&idle_cpu_knl),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT,	&idle_cpu_bxt),