Commit 1c2b4812 authored by Stefan Chulski's avatar Stefan Chulski Committed by David S. Miller
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doc: marvell: add CM3 address space and PPv2.3 description 



Patch adds CM3 address space and PPv2.3 description.

Signed-off-by: default avatarStefan Chulski <stefanc@marvell.com>
Acked-by: default avatarMarcin Wojtas <mw@semihalf.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f2fa0e5e

Documentation/devicetree/bindings/net/marvell-pp2.txt

+4 −2
Original line number Diff line number Diff line 
* Marvell Armada 375 Ethernet Controller (PPv2.1)

  Marvell Armada 7K/8K Ethernet Controller (PPv2.2)

  Marvell CN913X Ethernet Controller (PPv2.3)



Required properties:
@@ -12,10 +13,11 @@ Required properties: 
	- common controller registers

	- LMS registers

	- one register area per Ethernet port

  For "marvell,armada-7k-pp2", must contain the following register

  For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the following register

  sets:

	- packet processor registers

	- networking interfaces registers

	- CM3 address space used for TX Flow Control



- clocks: pointers to the reference clocks for this device, consequently:

	- main controller clock (for both armada-375-pp2 and armada-7k-pp2)
@@ -81,7 +83,7 @@ Example for marvell,armada-7k-pp2: 


cpm_ethernet: ethernet@0 {

	compatible = "marvell,armada-7k-pp22";

	reg = <0x0 0x100000>, <0x129000 0xb000>;

	reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;

	clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,

		 <&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>;

	clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";