Loading arch/loongarch/kernel/setup.c +26 −2 Original line number Diff line number Diff line Loading @@ -184,12 +184,14 @@ bool wc_enabled = false; EXPORT_SYMBOL(wc_enabled); static int wc_arg = -1; static int __init setup_writecombine(char *p) { if (!strcmp(p, "on")) wc_enabled = true; wc_arg = true; else if (!strcmp(p, "off")) wc_enabled = false; wc_arg = false; else pr_warn("Unknown writecombine setting \"%s\".\n", p); Loading Loading @@ -371,6 +373,26 @@ static void __init bootcmdline_init(char **cmdline_p) *cmdline_p = boot_command_line; } static void __init writecombine_detect(void) { u64 cpuname; if (wc_arg >= 0) { wc_enabled = wc_arg; return; } cpuname = iocsr_read64(LOONGARCH_IOCSR_CPUNAME); switch (cpuname) { case 0x0000303030364333: wc_enabled = true; break; default: break; } } void __init platform_init(void) { arch_reserve_vmcore(); Loading @@ -394,6 +416,8 @@ void __init platform_init(void) smbios_parse(); pr_info("The BIOS Version: %s\n", b_info.bios_version); writecombine_detect(); pr_info("WriteCombine: %s\n", wc_enabled ? "on":"off"); efi_runtime_init(); } Loading include/drm/drm_cache.h +1 −1 Original line number Diff line number Diff line Loading @@ -74,7 +74,7 @@ static inline bool drm_arch_can_wc_memory(void) * cache coherency machanism. This means WUC can only used for write-only * memory regions. */ return false; return wc_enabled; #else return true; #endif Loading Loading
arch/loongarch/kernel/setup.c +26 −2 Original line number Diff line number Diff line Loading @@ -184,12 +184,14 @@ bool wc_enabled = false; EXPORT_SYMBOL(wc_enabled); static int wc_arg = -1; static int __init setup_writecombine(char *p) { if (!strcmp(p, "on")) wc_enabled = true; wc_arg = true; else if (!strcmp(p, "off")) wc_enabled = false; wc_arg = false; else pr_warn("Unknown writecombine setting \"%s\".\n", p); Loading Loading @@ -371,6 +373,26 @@ static void __init bootcmdline_init(char **cmdline_p) *cmdline_p = boot_command_line; } static void __init writecombine_detect(void) { u64 cpuname; if (wc_arg >= 0) { wc_enabled = wc_arg; return; } cpuname = iocsr_read64(LOONGARCH_IOCSR_CPUNAME); switch (cpuname) { case 0x0000303030364333: wc_enabled = true; break; default: break; } } void __init platform_init(void) { arch_reserve_vmcore(); Loading @@ -394,6 +416,8 @@ void __init platform_init(void) smbios_parse(); pr_info("The BIOS Version: %s\n", b_info.bios_version); writecombine_detect(); pr_info("WriteCombine: %s\n", wc_enabled ? "on":"off"); efi_runtime_init(); } Loading
include/drm/drm_cache.h +1 −1 Original line number Diff line number Diff line Loading @@ -74,7 +74,7 @@ static inline bool drm_arch_can_wc_memory(void) * cache coherency machanism. This means WUC can only used for write-only * memory regions. */ return false; return wc_enabled; #else return true; #endif Loading