Commit 1bd9dfec authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Paolo Bonzini
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KVM: x86: Do not block APIC write for non ICR registers 



The commit 5413bcba ("KVM: x86: Add support for vICR APIC-write
VM-Exits in x2APIC mode") introduces logic to prevent APIC write
for offset other than ICR in kvm_apic_write_nodecode() function.
This breaks x2AVIC support, which requires KVM to trap and emulate
x2APIC MSR writes.

Therefore, removes the warning and modify to logic to allow MSR write.

Fixes: 5413bcba ("KVM: x86: Add support for vICR APIC-write VM-Exits in x2APIC mode")
Cc: Zeng Guang <guang.zeng@intel.com>
Suggested-by: default avatarSean Christopherson <seanjc@google.com>
Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Message-Id: <20220725053356.4275-1-suravee.suthikulpanit@amd.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 0a8735a6

arch/x86/kvm/lapic.c

+11 −11
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ static bool lapic_timer_advance_dynamic __read_mostly; 
/* step-by-step approximation to mitigate fluctuation */

#define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8

static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data);

static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data);



static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val)

{
@@ -2283,21 +2284,20 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) 
	struct kvm_lapic *apic = vcpu->arch.apic;

	u64 val;



	if (apic_x2apic_mode(apic)) {

	if (apic_x2apic_mode(apic))

		kvm_lapic_msr_read(apic, offset, &val);

	else

		val = kvm_lapic_get_reg(apic, offset);



	/*

		 * When guest APIC is in x2APIC mode and IPI virtualization

		 * is enabled, accessing APIC_ICR may cause trap-like VM-exit

		 * on Intel hardware. Other offsets are not possible.

	 * ICR is a single 64-bit register when x2APIC is enabled.  For legacy

	 * xAPIC, ICR writes need to go down the common (slightly slower) path

	 * to get the upper half from ICR2.

	 */

		if (WARN_ON_ONCE(offset != APIC_ICR))

			return;



		kvm_lapic_msr_read(apic, offset, &val);

	if (apic_x2apic_mode(apic) && offset == APIC_ICR) {

		kvm_apic_send_ipi(apic, (u32)val, (u32)(val >> 32));

		trace_kvm_apic_write(APIC_ICR, val);

	} else {

		val = kvm_lapic_get_reg(apic, offset);



		/* TODO: optimize to just emulate side effect w/o one more write */

		kvm_lapic_reg_write(apic, offset, (u32)val);

	}