Commit 1bd1d10d authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Matthias Brugger
Browse files

arm64: dts: mediatek: mt8195: Use P1 clocks for PCIe1 controller 



Despite there being some flexibility regarding the P0/P1 connections,
especially for TL and PERI, we must use P1 clocks on pcie1 otherwise
we'll be dealing with unclocked access.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221214131117.108008-1-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 4f5fc078

arch/arm64/boot/dts/mediatek/mt8195.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -1258,9 +1258,9 @@ 


			clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,

				 <&clk26m>,

				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,

				 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,

				 <&clk26m>,

				 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,

				 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,

				 /* Designer has connect pcie1 with peri_mem_p0 clock */

				 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;

			clock-names = "pl_250m", "tl_26m", "tl_96m",