Commit 1ba9ddea authored by David E. Box's avatar David E. Box Committed by Jason Zeng
Browse files

PCI: Add #defines for accessing PCIe DVSEC fields 

mainline inclusion
from mainline-v5.17-rc1
commit 80b3485f
category: bugfix
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8C8B4
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=80b3485f7d7bdb2468f2a9d6a346a1132d248309



-------------------------------------

Intel-SIG: commit 80b3485f PCI: Add #defines for accessing PCIe DVSEC fields
Backport SPR and EMR IOMMU PCIe related upstream bugfixes to kernel 5.10.

Add #defines for accessing Vendor ID, Revision, Length, and ID offsets
in the Designated Vendor Specific Extended Capability (DVSEC). Defined
in PCIe r5.0, sec 7.9.6.

Reviewed-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: default avatarDavid E. Box <david.e.box@linux.intel.com>
Link: https://lore.kernel.org/r/20211208015015.891275-2-david.e.box@linux.intel.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 80b3485f)
Signed-off-by: default avatarEthan Zhao <haifeng.zhao@linux.intel.com>
parent bb21c3ff

include/uapi/linux/pci_regs.h

+4 −0
Original line number Diff line number Diff line
@@ -1082,7 +1082,11 @@ 


/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */

#define PCI_DVSEC_HEADER1		0x4 /* Designated Vendor-Specific Header1 */

#define  PCI_DVSEC_HEADER1_VID(x)	((x) & 0xffff)

#define  PCI_DVSEC_HEADER1_REV(x)	(((x) >> 16) & 0xf)

#define  PCI_DVSEC_HEADER1_LEN(x)	(((x) >> 20) & 0xfff)

#define PCI_DVSEC_HEADER2		0x8 /* Designated Vendor-Specific Header2 */

#define  PCI_DVSEC_HEADER2_ID(x)		((x) & 0xffff)



/* Data Link Feature */

#define PCI_DLF_CAP		0x04	/* Capabilities Register */